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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qca-wifi-host-cmn / afd6e88b36e1e198941ab6a426abaa11766b8663 / . / hif / src / ce / ce_reg.h
blob: 4dfcd7141f90701d9dd6065aa46fcb02dab5d139 [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1/*
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame^]2 * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28#ifndef __CE_REG_H__
29#define __CE_REG_H__
30
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]31#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
32 - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
33
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]34#define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
35#define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
36#define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
37#define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
38#define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
39#define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
40#define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
41#define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
42
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame^]43#define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
44#define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
45#define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
46#define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
47#define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
48#define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
49#define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
50#define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
51#define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
52#define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
53#define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
54#define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
55#define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
56#define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
57#define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
58#define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
59#define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
60#define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
61#define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
62#define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
63#define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
64#define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
65#define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
66#define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
67#define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
68#define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
69#define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
70#define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
71#define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
72#define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
73#define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
74#define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
75#define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
76#define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
77#define SHADOW_ADDRESS10 \
78 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
79#define SHADOW_ADDRESS11 \
80 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
81#define SHADOW_ADDRESS12 \
82 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
83#define SHADOW_ADDRESS13 \
84 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
85#define SHADOW_ADDRESS14 \
86 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
87#define SHADOW_ADDRESS15 \
88 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
89#define SHADOW_ADDRESS16 \
90 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
91#define SHADOW_ADDRESS17 \
92 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
93#define SHADOW_ADDRESS18 \
94 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
95#define SHADOW_ADDRESS19 \
96 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
97#define SHADOW_ADDRESS20 \
98 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
99#define SHADOW_ADDRESS21 \
100 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
101#define SHADOW_ADDRESS22 \
102 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
103#define SHADOW_ADDRESS23 \
104 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]105
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame^]106#define SHADOW_ADDRESS(i) \
107 (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]108
109#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
110 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
111#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
112 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
113#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
114 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
115#define HOST_IS_DST_RING_LOW_WATERMARK_MASK \
116 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
117#define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS)
118#define HOST_IS_COPY_COMPLETE_MASK \
119 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
120#define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
121#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
122 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]123#define CE_DDR_ADDRESS_FOR_RRI_LOW \
124 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
125#define CE_DDR_ADDRESS_FOR_RRI_HIGH \
126 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]127#define HOST_IE_COPY_COMPLETE_MASK \
128 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
129#define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
130#define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
131#define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS)
132#define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
133#define CE_CTRL1_DMAX_LENGTH_MASK \
134 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
135#define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS)
136#define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
137#define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS)
138#define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER)
139#define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS)
140#define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
141#define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA)
142#define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
143#define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS)
144#define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
145#define MISC_IS_DST_ADDR_ERR_MASK \
146 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
147#define MISC_IS_SRC_LEN_ERR_MASK \
148 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
149#define MISC_IS_DST_MAX_LEN_VIO_MASK \
150 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
151#define MISC_IS_DST_RING_OVERFLOW_MASK \
152 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
153#define MISC_IS_SRC_RING_OVERFLOW_MASK \
154 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
155#define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
156#define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
157#define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
158#define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
159#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
160 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
161#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
162 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame^]163#define CE_CTRL1_DMAX_LENGTH_LSB \
164 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]165#define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]166#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
167 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
168#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
169 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
170#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
171 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
172#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
173 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
174#define WLAN_DEBUG_INPUT_SEL_OFFSET \
175 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
176#define WLAN_DEBUG_INPUT_SEL_SRC_MSB \
177 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
178#define WLAN_DEBUG_INPUT_SEL_SRC_LSB \
179 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
180#define WLAN_DEBUG_INPUT_SEL_SRC_MASK \
181 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
182#define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
183#define WLAN_DEBUG_CONTROL_ENABLE_MSB \
184 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
185#define WLAN_DEBUG_CONTROL_ENABLE_LSB \
186 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
187#define WLAN_DEBUG_CONTROL_ENABLE_MASK \
188 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
189#define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
190#define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
191#define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
192#define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
193#define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
194#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \
195 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
196#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \
197 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
198#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \
199 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
200#define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
201#define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
202#define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
Manikandan Mohanafd6e882017-04-07 17:46:41 -0700[diff] [blame^]203#define CE_WRAPPER_DEBUG_OFFSET \
204 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
205#define CE_WRAPPER_DEBUG_SEL_MSB \
206 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
207#define CE_WRAPPER_DEBUG_SEL_LSB \
208 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
209#define CE_WRAPPER_DEBUG_SEL_MASK \
210 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]211#define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET)
212#define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
213#define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
214#define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
215#define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
Venkateswara Swamy Bandaru2aa2c692016-09-20 20:25:39 +0530[diff] [blame]216#define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]217#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
218
219#define SRC_WATERMARK_LOW_SET(x) \
220 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
221#define SRC_WATERMARK_HIGH_SET(x) \
222 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
223#define DST_WATERMARK_LOW_SET(x) \
224 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
225#define DST_WATERMARK_HIGH_SET(x) \
226 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
227#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
228 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
229 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
230#define CE_CTRL1_DMAX_LENGTH_SET(x) \
231 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
232#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
233 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
234 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
235#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
236 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
237 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
238#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \
239 (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \
240 WLAN_DEBUG_INPUT_SEL_SRC_LSB)
241#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \
242 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \
243 WLAN_DEBUG_INPUT_SEL_SRC_MASK)
244#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \
245 (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \
246 WLAN_DEBUG_CONTROL_ENABLE_LSB)
247#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \
248 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \
249 WLAN_DEBUG_CONTROL_ENABLE_MASK)
250#define WLAN_DEBUG_OUT_DATA_GET(x) \
251 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
252#define WLAN_DEBUG_OUT_DATA_SET(x) \
253 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
254#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \
255 (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \
256 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
257#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \
258 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \
259 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
260#define AMBA_DEBUG_BUS_SEL_GET(x) \
261 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
262#define AMBA_DEBUG_BUS_SEL_SET(x) \
263 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
264#define CE_WRAPPER_DEBUG_SEL_GET(x) \
265 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
266#define CE_WRAPPER_DEBUG_SEL_SET(x) \
267 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
268#define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
269#define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
270
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]271uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]272 uint32_t CE_ctrl_addr);
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]273uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]274 uint32_t CE_ctrl_addr);
275
276#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(paddr_rri_on_ddr)\
277 & (uint64_t)(0xFFFFFFFF)))
278#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(paddr_rri_on_ddr)\
279 & (uint64_t)(0xF00000000))>>32))
280
281#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
Hardik Kantilal Patel34373922016-07-13 22:14:14 +0530[diff] [blame]282 ((scn->vaddr_rri_on_ddr) + COPY_ENGINE_ID(CE_ctrl_addr))
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]283
284#define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
285#define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
286
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]287#define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
288 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
289#define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
290 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
291
Houston Hoffman5998d5f2015-12-03 13:25:05 -0800[diff] [blame]292#ifdef ADRASTEA_RRI_ON_DDR
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]293#ifdef SHADOW_REG_DEBUG
294#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
295 DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
296#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
297 DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)
298#else
299#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
300 SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
301#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
302 DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
303#endif
304
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]305unsigned int hif_get_src_ring_read_index(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]306 uint32_t CE_ctrl_addr);
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]307unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn,
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]308 uint32_t CE_ctrl_addr);
309
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]310#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
311 hif_get_src_ring_read_index(scn, CE_ctrl_addr)
312#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
313 hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
314#else
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]315#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]316 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]317#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]318 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr)
Houston Hoffman5998d5f2015-12-03 13:25:05 -0800[diff] [blame]319
320/**
321 * if RRI on DDR is not enabled, get idx from ddr defaults to
322 * using the register value & force wake must be used for
323 * non interrupt processing.
324 */
325#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
326 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]327#endif
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]328
329#define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
330 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
331
332#define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
333 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr))
334
335#define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
336 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH)
337
338#define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \
339 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n))
340
341#define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \
342 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
343 (A_TARGET_READ(scn, (CE_ctrl_addr) + \
344 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \
345 CE_CTRL1_DMAX_LENGTH_SET(n))
346
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]347#define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \
348 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
349 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
350 | CE_CTRL1_IDX_UPD_EN))
351
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]352#define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \
353 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
354
355#define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \
356 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n)
357
358#define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \
359 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr))
360
361#define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
362 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr))
363
364#define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \
365 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data))
366
367#define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \
368 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val)
369
370#define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \
371 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS)
372
373#define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
374 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
Houston Hoffman6296c3e2016-07-12 18:43:32 -0700[diff] [blame]375 (A_TARGET_READ(scn, \
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]376 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
377 & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \
378 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n))
379
380#define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
381 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \
Houston Hoffman6296c3e2016-07-12 18:43:32 -0700[diff] [blame]382 (A_TARGET_READ(scn, \
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]383 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
384 & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
385 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
386
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]387
388#define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
389 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
390
391#define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
392 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr))
393
394#define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
395 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH)
396
397#define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \
398 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n))
399
400#define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
401 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
402 (A_TARGET_READ(scn, \
403 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
404 & ~SRC_WATERMARK_HIGH_MASK) | \
405 SRC_WATERMARK_HIGH_SET(n))
406
407#define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
408 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
409 (A_TARGET_READ(scn, \
410 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
411 & ~SRC_WATERMARK_LOW_MASK) | \
412 SRC_WATERMARK_LOW_SET(n))
413
414#define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
415 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
416 (A_TARGET_READ(scn, \
417 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
418 & ~DST_WATERMARK_HIGH_MASK) | \
419 DST_WATERMARK_HIGH_SET(n))
420
421#define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
422 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
423 (A_TARGET_READ(scn, \
424 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
425 & ~DST_WATERMARK_LOW_MASK) | \
426 DST_WATERMARK_LOW_SET(n))
427
428#define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \
429 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
430 A_TARGET_READ(scn, \
431 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
432 HOST_IE_COPY_COMPLETE_MASK)
433
434#define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \
435 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
436 A_TARGET_READ(scn, \
437 (CE_ctrl_addr) + HOST_IE_ADDRESS) \
438 & ~HOST_IE_COPY_COMPLETE_MASK)
439
440#define CE_BASE_ADDRESS(CE_id) \
441 CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \
442 CE0_BASE_ADDRESS)*(CE_id))
443
444#define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \
445 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
446 A_TARGET_READ(scn, \
447 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
448 CE_WATERMARK_MASK)
449
450#define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \
451 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
452 A_TARGET_READ(scn, \
453 (CE_ctrl_addr) + HOST_IE_ADDRESS) \
454 & ~CE_WATERMARK_MASK)
455
456#define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \
457 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \
458 A_TARGET_READ(scn, \
459 (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK)
460
461#define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \
462 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS)
463
464#define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \
465 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS)
466
467#define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \
468 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
469
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]470#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
471 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
472 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
473 HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
474
475#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
476 MISC_IS_DST_ADDR_ERR_MASK | \
477 MISC_IS_SRC_LEN_ERR_MASK | \
478 MISC_IS_DST_MAX_LEN_VIO_MASK | \
479 MISC_IS_DST_RING_OVERFLOW_MASK | \
480 MISC_IS_SRC_RING_OVERFLOW_MASK)
481
482#define CE_SRC_RING_TO_DESC(baddr, idx) \
483 (&(((struct CE_src_desc *)baddr)[idx]))
484#define CE_DEST_RING_TO_DESC(baddr, idx) \
485 (&(((struct CE_dest_desc *)baddr)[idx]))
486
487/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
488#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
489 (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
490
491#define CE_RING_IDX_INCR(nentries_mask, idx) \
492 (((idx) + 1) & (nentries_mask))
493
494#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
495 (((idx) + (num)) & (nentries_mask))
496
497#define CE_INTERRUPT_SUMMARY(scn) \
498 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
499 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
500 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
501
Sanjay Devnanicdab59e2015-11-12 14:43:58 -0800[diff] [blame]502#define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \
503 (A_TARGET_READ(scn, \
504 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW))
505
506#define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \
507 (A_TARGET_READ(scn, \
508 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH))
509
510#define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \
511 (A_TARGET_WRITE(scn, \
512 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \
513 val))
514
515#define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \
516 (A_TARGET_WRITE(scn, \
517 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \
518 val))
519
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]520/*Macro to increment CE packet errors*/
521#define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \
522 do { if (_ce_ecode == CE_RING_DELTA_FAIL) \
523 (_scn->pkt_stats.ce_ring_delta_fail_count) \
524 += 1; } while (0)
525
526/* Given a Copy Engine's ID, determine the interrupt number for that
527 * copy engine's interrupts.
528 */
529#define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id))
530#define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE)
531#define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS)
532#define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS)
533
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]534
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]535#ifdef ADRASTEA_SHADOW_REGISTERS
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]536#define NUM_SHADOW_REGISTERS 24
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]537u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
538u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr);
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]539#endif
540
541
542#ifdef ADRASTEA_SHADOW_REGISTERS
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]543#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
544 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n)
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]545#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
546 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n)
547
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]548#else
549
550#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
551 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]552#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
553 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]554#endif
555
Houston Hoffman47808172016-05-06 10:04:21 -0700[diff] [blame]556/* The write index read is only needed durring initialization because
557 * we keep track of the index that was last written. Thus the register
558 * is the only hardware supported location to read the initial value from.
559 */
560#define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
561 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS)
562#define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \
563 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS)
564
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]565#endif /* __CE_REG_H__ */