tree 87b49540046ba877339b366fb664121d839a5513
parent febc981b59229ab93b7d869001fb451ac1448be1
author sheenam monga <shebala@codeaurora.org> 1576580665 +0530
committer nshrivas <nshrivas@codeaurora.org> 1576959305 -0800

qcacld-3.0: Handle bus bandwidth in start and stop modules

Currently, bus bandwidth is initialized and deinitialized in
different memory domains which may cause leaks due to async bandwidth
init and deinit.

Fix is to initialize and de-initialize bus bandwidth in active domain.

Change-Id: I67cf9ecdd47c8f3ca6e9b272ca379f0cac9a6c7b
CRs-Fixed: 2568881