[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6
Summary:
There is no change to the restrictions, just the result register is stored
once in the encoding rather than twice. The rt field is zero in
MIPS32r6/MIPS64r6.
Depends on D4119
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4120
llvm-svn: 211019
diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll
new file mode 100644
index 0000000..81fb2b4
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/countleading.ll
@@ -0,0 +1,90 @@
+; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
+; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+
+; Prefixes:
+; ALL - All
+; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
+; MIPS64-GT-R1 - MIPS64r1 and above
+
+define i32 @ctlz_i32(i32 %X) nounwind readnone {
+entry:
+; ALL-LABEL: ctlz_i32:
+
+; MIPS4-NOT: clz
+
+; MIPS32-GT-R1: clz $2, $4
+
+; MIPS64-GT-R1: clz $2, $4
+
+ %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
+ ret i32 %tmp1
+}
+
+declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
+
+define i32 @ctlo_i32(i32 %X) nounwind readnone {
+entry:
+; ALL-LABEL: ctlo_i32:
+
+; MIPS4-NOT: clo
+
+; MIPS32-GT-R1: clo $2, $4
+
+; MIPS64-GT-R1: clo $2, $4
+
+ %neg = xor i32 %X, -1
+ %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
+ ret i32 %tmp1
+}
+
+define i64 @ctlz_i64(i64 %X) nounwind readnone {
+entry:
+; ALL-LABEL: ctlz_i64:
+
+; MIPS4-NOT: dclz
+
+; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
+; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
+; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
+; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
+; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R2]], $5
+; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R1]], $5
+; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
+; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
+
+; MIPS64-GT-R1: dclz $2, $4
+
+ %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
+ ret i64 %tmp1
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
+
+define i64 @ctlo_i64(i64 %X) nounwind readnone {
+entry:
+; ALL-LABEL: ctlo_i64:
+
+; MIPS4-NOT: dclo
+
+; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4
+; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5
+; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
+; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1
+; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]]
+; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]]
+; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
+; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
+; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
+; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
+
+; MIPS64-GT-R1: dclo $2, $4
+
+ %neg = xor i64 %X, -1
+ %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
+ ret i64 %tmp1
+}
diff --git a/llvm/test/CodeGen/Mips/mips64countleading.ll b/llvm/test/CodeGen/Mips/mips64countleading.ll
deleted file mode 100644
index 252f323..0000000
--- a/llvm/test/CodeGen/Mips/mips64countleading.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
-
-define i64 @t1(i64 %X) nounwind readnone {
-entry:
-; CHECK-LABEL: t1:
-; MIPS4-NOT: dclz
-; MIPS64: dclz
- %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
- ret i64 %tmp1
-}
-
-declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
-
-define i64 @t3(i64 %X) nounwind readnone {
-entry:
-; CHECK-LABEL: t3:
-; MIPS4-NOT: dclo
-; MIPS64: dclo
- %neg = xor i64 %X, -1
- %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
- ret i64 %tmp1
-}
-
diff --git a/llvm/test/CodeGen/Mips/mips64instrs.ll b/llvm/test/CodeGen/Mips/mips64instrs.ll
index cf0a097..ed617be 100644
--- a/llvm/test/CodeGen/Mips/mips64instrs.ll
+++ b/llvm/test/CodeGen/Mips/mips64instrs.ll
@@ -1,5 +1,7 @@
-; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
-; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s
+; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s
+; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s
@gll0 = common global i64 0, align 8
@gll1 = common global i64 0, align 8
@@ -87,7 +89,10 @@
define i64 @f12(i64 %a, i64 %b) nounwind readnone {
entry:
; ALL-LABEL: f12:
-; ALL: mult ${{[45]}}, ${{[45]}}
+
+; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
+; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
+
%mul = mul nsw i64 %b, %a
ret i64 %mul
}
@@ -95,7 +100,10 @@
define i64 @f13(i64 %a, i64 %b) nounwind readnone {
entry:
; ALL-LABEL: f13:
-; ALL: mult ${{[45]}}, ${{[45]}}
+
+; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
+; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
+
%mul = mul i64 %b, %a
ret i64 %mul
}
@@ -107,9 +115,14 @@
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
-; ALL: ddiv $zero, $[[T0]], $[[T1]]
-; ALL: teq $[[T1]], $zero, 7
-; ALL: mflo $2
+
+; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
+; ACCMULDIV: teq $[[T1]], $zero, 7
+; ACCMULDIV: mflo $2
+
+; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
+; GPRMULDIV: teq $[[T1]], $zero, 7
+
%0 = load i64* @gll0, align 8
%1 = load i64* @gll1, align 8
%div = sdiv i64 %0, %1
@@ -123,9 +136,14 @@
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
-; ALL: ddivu $zero, $[[T0]], $[[T1]]
-; ALL: teq $[[T1]], $zero, 7
-; ALL: mflo $2
+
+; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
+; ACCMULDIV: teq $[[T1]], $zero, 7
+; ACCMULDIV: mflo $2
+
+; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
+; GPRMULDIV: teq $[[T1]], $zero, 7
+
%0 = load i64* @gll0, align 8
%1 = load i64* @gll1, align 8
%div = udiv i64 %0, %1
@@ -135,9 +153,14 @@
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
entry:
; ALL-LABEL: f16:
-; ALL: ddiv $zero, $4, $5
-; ALL: teq $5, $zero, 7
-; ALL: mfhi $2
+
+; ACCMULDIV: ddiv $zero, $4, $5
+; ACCMULDIV: teq $5, $zero, 7
+; ACCMULDIV: mfhi $2
+
+; GPRMULDIV: dmod $2, $4, $5
+; GPRMULDIV: teq $5, $zero, 7
+
%rem = srem i64 %a, %b
ret i64 %rem
}
@@ -145,9 +168,14 @@
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
entry:
; ALL-LABEL: f17:
-; ALL: ddivu $zero, $4, $5
-; ALL: teq $5, $zero, 7
-; ALL: mfhi $2
+
+; ACCMULDIV: ddivu $zero, $4, $5
+; ACCMULDIV: teq $5, $zero, 7
+; ACCMULDIV: mfhi $2
+
+; GPRMULDIV: dmodu $2, $4, $5
+; GPRMULDIV: teq $5, $zero, 7
+
%rem = urem i64 %a, %b
ret i64 %rem
}
@@ -161,7 +189,8 @@
; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
; MIPS4-NOT: dclz
-; MIPS64: dclz $2, $4
+; HAS-DCLO: dclz $2, $4
+
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
@@ -173,7 +202,8 @@
; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
; MIPS4-NOT: dclo
-; MIPS64: dclo $2, $4
+; HAS-DCLO: dclo $2, $4
+
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1