commit 006bb04f3ab11fabf0d7f01149ce687fb508125a
author Nate Begeman <natebegeman@mac.com> Thu Dec 01 04:51:06 2005 +0000
committer Nate Begeman <natebegeman@mac.com> Thu Dec 01 04:51:06 2005 +0000
tree 13e8f62ec30ed542e68ffa4a23ce28b5f2ce6ad1
parent aa5f8f2a262857da781e23fe919e374e98a0151a

Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.

llvm-svn: 24563

llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index f250a7b..c1a7f47 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -1208,7 +1208,7 @@
         // Pick the register class of the right type that contains this physreg.
         for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
              E = MRI.regclass_end(); I != E; ++I)
-          if ((*I)->getType() == Node->getValueType(0) &&
+          if ((*I)->hasType(Node->getValueType(0)) &&
               (*I)->contains(SrcReg)) {
             TRC = *I;
             break;