commit 0084adc5165622ea838f9af1e5a0559cd128b483
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Apr 30 19:08:16 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Apr 30 19:08:16 2018 +0000
tree a24f460232a0d35c1eca0b9045b4a22645aa2866
parent 45c7205b617895a96073da30aabfdbae2bb8651c

AMDGPU: Add Vega12 and Vega20

Changes by
  Matt Arsenault
  Konstantin Zhuravlyov

llvm-svn: 331215

llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index a346e40..61cbba4 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -100,6 +100,7 @@
 
       case AMDGPU::V_MAC_F32_e64:
       case AMDGPU::V_MAC_F16_e64:
+      case AMDGPU::V_FMAC_F32_e64:
         if (!isVGPR(Src2, TRI, MRI) ||
             TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
           return false;