[PowerPC] Pretty-print CR bits the way the binutils disassembler does
This patch just adds printing of CR bit registers in a more human-readable
form akin to that used by the GNU binutils.
Differential Revision: https://reviews.llvm.org/D31494
llvm-svn: 309001
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
index 3ad4328..d71460b 100644
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -1,11 +1,15 @@
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
-; RUN: < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN: < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
-; RUN: < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp
-; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN: < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN: -check-prefix=P9BE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN: -check-prefix=P9LE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN: -check-prefix=P8BE -implicit-check-not frsp
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN: -check-prefix=P8LE -implicit-check-not frsp
; This test case comes from the following C test case (included as it may be
; slightly more readable than the LLVM IR.
diff --git a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
index 5fe69eb..a8ed09c 100644
--- a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
@@ -122,7 +122,7 @@
; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
-; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
+; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll
index c8707bda..608f036 100644
--- a/llvm/test/CodeGen/PowerPC/expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll
@@ -12,7 +12,7 @@
; CHECK-LABEL: @testExpandISELToIfElse
; CHECK: addi r5, r3, 1
; CHECK-NEXT: cmpwi cr0, r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
@@ -32,7 +32,7 @@
; CHECK-LABEL: @testExpandISELToIf
; CHECK: cmpwi r3, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK-NEXT: blr
; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r3, r4, 0
@@ -48,7 +48,7 @@
; CHECK-LABEL: @testExpandISELToElse
; CHECK: cmpwi r3, 0
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bclr 12, gt, 0
; CHECK: ori r3, r4, 0
; CHECK-NEXT: blr
}
@@ -95,7 +95,7 @@
; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs
; CHECK: cmpwi r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: ori r12, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -121,7 +121,7 @@
; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0
; CHECK-NEXT: ori r12, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
@@ -148,7 +148,7 @@
; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r5, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
@@ -176,7 +176,7 @@
; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
; CHECK: cmpwi cr0, r7, 0
-; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
+; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r4, r3, 0
diff --git a/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
index 5a507e9..7da9789 100644
--- a/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
+++ b/llvm/test/CodeGen/PowerPC/logic-ops-on-compares.ll
@@ -18,7 +18,7 @@
; CHECK-NEXT: srwi r6, r6, 5
; CHECK-NEXT: srwi r5, r5, 5
; CHECK-NEXT: or. r5, r6, r5
-; CHECK-NEXT: bc 4, 1
+; CHECK-NEXT: bc 4, gt
entry:
%tobool = icmp eq i32 %a, %b
%tobool1 = icmp eq i32 %b, 0
@@ -45,7 +45,7 @@
; CHECK: # BB#0: # %entry
; CHECK-NEXT: lwz r3, 0(r3)
; CHECK-NEXT: rldicl. r3, r3, 0, 63
-; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: bclr 12, eq, 0
; CHECK-NEXT: # BB#1: # %if.end29.thread136
; CHECK-NEXT: .LBB1_2: # %if.end29
entry:
@@ -77,7 +77,7 @@
; CHECK-NEXT: rldicl r6, r6, 58, 63
; CHECK-NEXT: rldicl r5, r5, 58, 63
; CHECK-NEXT: or. r5, r6, r5
-; CHECK-NEXT: bc 4, 1
+; CHECK-NEXT: bc 4, gt
entry:
%tobool = icmp eq i64 %a, %b
%tobool1 = icmp eq i64 %b, 0
@@ -104,7 +104,7 @@
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: rldicl. r3, r3, 0, 63
-; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: bclr 12, eq, 0
; CHECK-NEXT: # BB#1: # %if.end29.thread136
; CHECK-NEXT: .LBB3_2: # %if.end29
entry:
@@ -138,7 +138,7 @@
; CHECK-NEXT: subfe r6, r12, r4
; CHECK-NEXT: and r6, r7, r6
; CHECK-NEXT: or. r5, r6, r5
-; CHECK-NEXT: bc 4, 1
+; CHECK-NEXT: bc 4, gt
entry:
%tobool = icmp ne i64 %a, %b
%tobool1 = icmp ne i64 %b, 0
@@ -165,7 +165,7 @@
; CHECK: # BB#0: # %entry
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: andi. r3, r3, 1
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bclr 12, gt, 0
; CHECK-NEXT: # BB#1: # %if.end29.thread136
; CHECK-NEXT: .LBB5_2: # %if.end29
entry:
diff --git a/llvm/test/CodeGen/PowerPC/mtvsrdd.ll b/llvm/test/CodeGen/PowerPC/mtvsrdd.ll
index 1d6a355..a4a3d82 100644
--- a/llvm/test/CodeGen/PowerPC/mtvsrdd.ll
+++ b/llvm/test/CodeGen/PowerPC/mtvsrdd.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
-; RUN: < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
index 6d19d7f..f5319b2 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
@@ -20,8 +20,8 @@
; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \
-; RUN: -check-prefix=CHECK-P9 --implicit-check-not xxswapd
+; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \