[SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.
Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried). Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.
llvm-svn: 186683
diff --git a/llvm/test/CodeGen/SystemZ/and-01.ll b/llvm/test/CodeGen/SystemZ/and-01.ll
index f893148..3b230ba 100644
--- a/llvm/test/CodeGen/SystemZ/and-01.ll
+++ b/llvm/test/CodeGen/SystemZ/and-01.ll
@@ -1,6 +1,7 @@
; Test 32-bit ANDs in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/and-07.ll b/llvm/test/CodeGen/SystemZ/and-07.ll
new file mode 100644
index 0000000..2bdf97d
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/and-07.ll
@@ -0,0 +1,21 @@
+; Test the three-operand forms of AND.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check NRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: nrk %r2, %r3, %r4
+; CHECK: br %r14
+ %and = and i32 %b, %c
+ ret i32 %and
+}
+
+; Check that we can still use NR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: nr %r2, %r3
+; CHECK: br %r14
+ %and = and i32 %a, %b
+ ret i32 %and
+}
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll
index dd02828..6c7ba23 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-and-03.ll
@@ -1,6 +1,6 @@
; Test 32-bit atomic ANDs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check ANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
index be306a2..c511bd6 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
@@ -1,6 +1,6 @@
; Test 32-bit atomic NANDs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check NANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll
index 6386847..692b11c 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-or-03.ll
@@ -1,6 +1,6 @@
; Test 32-bit atomic ORs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check ORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
index 292de36..05754e7 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
@@ -1,6 +1,6 @@
; Test 32-bit atomic XORs.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
; Check XORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
diff --git a/llvm/test/CodeGen/SystemZ/or-01.ll b/llvm/test/CodeGen/SystemZ/or-01.ll
index ee0a392..23946d3 100644
--- a/llvm/test/CodeGen/SystemZ/or-01.ll
+++ b/llvm/test/CodeGen/SystemZ/or-01.ll
@@ -1,6 +1,7 @@
; Test 32-bit ORs in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/or-07.ll b/llvm/test/CodeGen/SystemZ/or-07.ll
new file mode 100644
index 0000000..f6848a1
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/or-07.ll
@@ -0,0 +1,21 @@
+; Test the three-operand forms of OR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check XRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: ork %r2, %r3, %r4
+; CHECK: br %r14
+ %or = or i32 %b, %c
+ ret i32 %or
+}
+
+; Check that we can still use OR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: or %r2, %r3
+; CHECK: br %r14
+ %or = or i32 %a, %b
+ ret i32 %or
+}
diff --git a/llvm/test/CodeGen/SystemZ/xor-01.ll b/llvm/test/CodeGen/SystemZ/xor-01.ll
index f9ba2eb..185d6bb 100644
--- a/llvm/test/CodeGen/SystemZ/xor-01.ll
+++ b/llvm/test/CodeGen/SystemZ/xor-01.ll
@@ -1,6 +1,7 @@
; Test 32-bit XORs in which the second operand is variable.
;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
declare i32 @foo()
diff --git a/llvm/test/CodeGen/SystemZ/xor-07.ll b/llvm/test/CodeGen/SystemZ/xor-07.ll
new file mode 100644
index 0000000..22deef6
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/xor-07.ll
@@ -0,0 +1,21 @@
+; Test the three-operand forms of XOR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check XRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: xrk %r2, %r3, %r4
+; CHECK: br %r14
+ %xor = xor i32 %b, %c
+ ret i32 %xor
+}
+
+; Check that we can still use XR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: xr %r2, %r3
+; CHECK: br %r14
+ %xor = xor i32 %a, %b
+ ret i32 %xor
+}