commit 0183c56c11b4a6c3a66b5b1db44aa3582fe7f15b
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 27 09:15:03 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 27 09:15:03 2018 +0000
tree 1b3458ca829355e7d8531f97f3ac749f1bcdad0b
parent 611dff423c05c97649838d0136fd9e1c0a6afd90

AMDGPU: Fix code size for return_to_epilog pseudo

llvm-svn: 338113

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 41c029c..6c85c92 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4753,12 +4753,12 @@
   if (DescSize != 0 && DescSize != 4)
     return DescSize;
 
+  if (isFixedSize(MI))
+    return DescSize;
+
   // 4-byte instructions may have a 32-bit literal encoded after them. Check
   // operands that coud ever be literals.
   if (isVALU(MI) || isSALU(MI)) {
-    if (isFixedSize(MI))
-      return DescSize;
-
     int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
     if (Src0Idx == -1)
       return 4; // No operands.