AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit insts
Summary:
The 32-bit instructions don't zero the high 16-bits like the 16-bit
instructions do.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26828
llvm-svn: 287342
diff --git a/llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll b/llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
new file mode 100644
index 0000000..cf384da
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN
+
+; GCN-LABEL: and_zext:
+; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
+define void @and_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
+ %id = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
+ %a = load i16, i16 addrspace(1)* %in
+ %b = load i16, i16 addrspace(1)* %ptr
+ %c = add i16 %a, %b
+ %val16 = and i16 %c, %a
+ %val32 = zext i16 %val16 to i32
+ store i32 %val32, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: or_zext:
+; GCN: v_or_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
+define void @or_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
+ %id = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
+ %a = load i16, i16 addrspace(1)* %in
+ %b = load i16, i16 addrspace(1)* %ptr
+ %c = add i16 %a, %b
+ %val16 = or i16 %c, %a
+ %val32 = zext i16 %val16 to i32
+ store i32 %val32, i32 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: xor_zext:
+; GCN: v_xor_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
+define void @xor_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
+ %id = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
+ %a = load i16, i16 addrspace(1)* %in
+ %b = load i16, i16 addrspace(1)* %ptr
+ %c = add i16 %a, %b
+ %val16 = xor i16 %c, %a
+ %val32 = zext i16 %val16 to i32
+ store i32 %val32, i32 addrspace(1)* %out
+ ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+attributes #1 = { nounwind readnone }