[PPC] Claim stack frame before storing into it, if no red zone is present
Unlike PPC64, PPC32/SVRV4 does not have red zone. In the absence of it
there is no guarantee that this part of the stack will not be modified
by any interrupt. To avoid this, make sure to claim the stack frame first
before storing into it.
This fixes https://llvm.org/bugs/show_bug.cgi?id=26519.
Differential Revision: https://reviews.llvm.org/D24093
llvm-svn: 280705
diff --git a/llvm/test/CodeGen/PowerPC/crsave.ll b/llvm/test/CodeGen/PowerPC/crsave.ll
index a079e7f..d7be2fd 100644
--- a/llvm/test/CodeGen/PowerPC/crsave.ll
+++ b/llvm/test/CodeGen/PowerPC/crsave.ll
@@ -14,8 +14,9 @@
ret i32 %1
}
-; PPC32: stw 31, -4(1)
+; PPC32-LABEL: test_cr2:
; PPC32: stwu 1, -32(1)
+; PPC32: stw 31, 28(1)
; PPC32: mfcr 12
; PPC32-NEXT: stw 12, 24(31)
; PPC32: lwz 12, 24(31)
@@ -43,8 +44,9 @@
ret i32 %1
}
-; PPC32: stw 31, -4(1)
+; PPC32-LABEL: test_cr234:
; PPC32: stwu 1, -32(1)
+; PPC32: stw 31, 28(1)
; PPC32: mfcr 12
; PPC32-NEXT: stw 12, 24(31)
; PPC32: lwz 12, 24(31)
diff --git a/llvm/test/CodeGen/PowerPC/empty-functions.ll b/llvm/test/CodeGen/PowerPC/empty-functions.ll
index 5f7a151..56db8f3 100644
--- a/llvm/test/CodeGen/PowerPC/empty-functions.ll
+++ b/llvm/test/CodeGen/PowerPC/empty-functions.ll
@@ -31,8 +31,8 @@
; LINUX-FP-NEXT: {{^}}.L[[BEGIN:.*]]:{{$}}
; LINUX-FP-NEXT: .cfi_startproc
; LINUX-FP-NEXT: {{^}}#
-; LINUX-FP-NEXT: stw 31, -4(1)
; LINUX-FP-NEXT: stwu 1, -16(1)
+; LINUX-FP-NEXT: stw 31, 12(1)
; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
; LINUX-FP-NEXT: .cfi_def_cfa_offset 16
; LINUX-FP-NEXT: {{^}}.L{{.*}}:{{$}}
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll
index bc1d0a5..dbfbc1c 100644
--- a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll
@@ -15,7 +15,8 @@
; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]:
; LARGE-BSS-NEXT: .long .LTOC-[[PB:\.L[0-9]+\$pb]]
; LARGE-BSS-NEXT: foo:
-; LARGE-BSS: stw 30, -8(1)
+; LARGE-BSS: stwu 1, -32(1)
+; LARGE-BSS: stw 30, 24(1)
; LARGE-BSS: bl [[PB]]
; LARGE-BSS-NEXT: [[PB]]:
; LARGE-BSS: mflr 30
diff --git a/llvm/test/CodeGen/PowerPC/ppc32-pic.ll b/llvm/test/CodeGen/PowerPC/ppc32-pic.ll
index 63f521c..5c33233 100644
--- a/llvm/test/CodeGen/PowerPC/ppc32-pic.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc32-pic.ll
@@ -13,8 +13,8 @@
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"PIC Level", i32 1}
; SMALL-BSS-LABEL:foo:
-; SMALL-BSS: stw 30, -8(1)
; SMALL-BSS: stwu 1, -32(1)
+; SMALL-BSS: stw 30, 24(1)
; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4
; SMALL-BSS: mflr 30
; SMALL-BSS-DAG: stw {{[0-9]+}}, 8(1)
diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll
index 1c93d66..00cd61d 100644
--- a/llvm/test/CodeGen/PowerPC/stack-realign.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll
@@ -77,22 +77,24 @@
; CHECK-FP: blr
; CHECK-32-LABEL: @goo
-; CHECK-32-DAG: mflr {{[0-9]+}}
+; CHECK-32-DAG: mflr [[LR:[0-9]+]]
; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
-; CHECK-32-DAG: stw 30, -8(1)
-; CHECK-32-DAG: mr 30, 1
-; CHECK-32-DAG: stw 0, 4(1)
+; CHECK-32-DAG: stw [[LR]], 4(1)
; CHECK-32-DAG: subfic 0, [[REG]], -64
; CHECK-32: stwux 1, 1, 0
+; CHECK-32: subf 0, 0, 1
+; CHECK-32: stw 30, -8(0)
+; CHECK-32: mr 30, 0
; CHECK-32-PIC-LABEL: @goo
-; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
+; CHECK-32-PIC-DAG: mflr [[LR:[0-9]+]]
; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
-; CHECK-32-PIC-DAG: stw 29, -12(1)
-; CHECK-32-PIC-DAG: mr 29, 1
-; CHECK-32-PIC-DAG: stw 0, 4(1)
+; CHECK-32-PIC-DAG: stw [[LR]], 4(1)
; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
; CHECK-32-PIC: stwux 1, 1, 0
+; CHECK-32-PIC: subf 0, 0, 1
+; CHECK-32-PIC: stw 29, -12(0)
+; CHECK-32-PIC-DAG: mr 29, 0
; The large-frame-size case.
define void @hoo(%struct.s* byval nocapture readonly %a) {
@@ -130,13 +132,15 @@
; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
-; CHECK-32-DAG: mflr {{[0-9]+}}
+; CHECK-32-DAG: mflr [[LR:[0-9]+]]
; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
-; CHECK-32-DAG: stw 30, -8(1)
-; CHECK-32-DAG: mr 30, 1
-; CHECK-32-DAG: stw 0, 4(1)
+; CHECK-32-DAG: stw [[LR]], 4(1)
; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
-; CHECK-32: stwux 1, 1, 0
+; CHECK-32: stwux 1, 1, 0
+; CHECK-32: subf 0, 0, 1
+; CHECK-32-DAG: stw 31, -4(0)
+; CHECK-32-DAG: stw 30, -8(0)
+; CHECK-32: mr 30, 0
; CHECK-32: blr
@@ -146,11 +150,12 @@
; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
-; CHECK-32-PIC-DAG: stw 29, -12(1)
-; CHECK-32-PIC-DAG: mr 29, 1
; CHECK-32-PIC-DAG: stw 0, 4(1)
; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
-; CHECK-32: stwux 1, 1, 0
+; CHECK-32-PIC: stwux 1, 1, 0
+; CHECK-32-PIC: stw 29, -12(0)
+; CHECK-32-PIC: subf 0, 0, 1
+; CHECK-32-PIC: mr 29, 0
; CHECK-32: blr