[Hexagon] Report error instead of crashing on wrong inline-asm constraints
llvm-svn: 316236
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 5a1b21a..bece022e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2979,46 +2979,47 @@
case 'r': // R0-R31
switch (VT.SimpleTy) {
default:
- llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
+ return {0u, nullptr};
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
case MVT::f32:
- return std::make_pair(0U, &Hexagon::IntRegsRegClass);
+ return {0u, &Hexagon::IntRegsRegClass};
case MVT::i64:
case MVT::f64:
- return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
+ return {0u, &Hexagon::DoubleRegsRegClass};
}
break;
case 'a': // M0-M1
- return std::make_pair(0U, &Hexagon::ModRegsRegClass);
+ if (VT != MVT::i32)
+ return {0u, nullptr};
+ return {0u, &Hexagon::ModRegsRegClass};
case 'q': // q0-q3
switch (VT.getSizeInBits()) {
default:
- llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
+ return {0u, nullptr};
case 512:
- return std::make_pair(0U, &Hexagon::HvxQRRegClass);
case 1024:
- return std::make_pair(0U, &Hexagon::HvxQRRegClass);
+ return {0u, &Hexagon::HvxQRRegClass};
}
break;
case 'v': // V0-V31
switch (VT.getSizeInBits()) {
default:
- llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size");
+ return {0u, nullptr};
case 512:
- return std::make_pair(0U, &Hexagon::HvxVRRegClass);
+ return {0u, &Hexagon::HvxVRRegClass};
case 1024:
if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
- return std::make_pair(0U, &Hexagon::HvxVRRegClass);
- return std::make_pair(0U, &Hexagon::HvxWRRegClass);
+ return {0u, &Hexagon::HvxVRRegClass};
+ return {0u, &Hexagon::HvxWRRegClass};
case 2048:
- return std::make_pair(0U, &Hexagon::HvxWRRegClass);
+ return {0u, &Hexagon::HvxWRRegClass};
}
break;
default:
- llvm_unreachable("Unknown asm register class");
+ return {0u, nullptr};
}
}