INC / DEC instructions have shorter code size than ADD32ri8, etc.
llvm-svn: 29194
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td
index 361b6ab..104d8797 100644
--- a/llvm/lib/Target/X86/X86InstrMMX.td
+++ b/llvm/lib/Target/X86/X86InstrMMX.td
@@ -22,9 +22,7 @@
class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasMMX]> {
- let Pattern = pattern;
-}
+ : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
// Some 'special' instructions
def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),