| commit | 033f99a2e567f0eebec6faa961025318f1e724f5 | [log] [tgz] |
|---|---|---|
| author | Tim Renouf <tpr.llvm@botech.co.uk> | Fri Mar 22 10:11:21 2019 +0000 |
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | Fri Mar 22 10:11:21 2019 +0000 |
| tree | 5619a489ebfc96ad8d476553cd1ffc8425a9cb12 | |
| parent | f8c785bf12136fb6590a144ff1edd3bc9be61ccf [diff] [blame] |
[AMDGPU] Added v5i32 and v5f32 register classes They are not used by anything yet, but a subsequent commit will start using them for image ops that return 5 dwords. Differential Revision: https://reviews.llvm.org/D58903 Change-Id: I63e1904081e39a6d66e4eb96d51df25ad399d271 llvm-svn: 356735
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 3e1cf68..b397554 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -822,6 +822,10 @@ case AMDGPU::SReg_128RegClassID: case AMDGPU::VReg_128RegClassID: return 128; + case AMDGPU::SGPR_160RegClassID: + case AMDGPU::SReg_160RegClassID: + case AMDGPU::VReg_160RegClassID: + return 160; case AMDGPU::SReg_256RegClassID: case AMDGPU::VReg_256RegClassID: return 256;