WebAssembly: start instructions
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.
Test Plan: ninja check
Reviewers: sunfish
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D10880
llvm-svn: 241211
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td
index f5e2564..a123bf6 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.td
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.td
@@ -22,8 +22,8 @@
// WebAssembly Subtarget features.
//===----------------------------------------------------------------------===//
-def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true",
- "Enable SIMD">;
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
+ "Enable 128-bit SIMD">;
//===----------------------------------------------------------------------===//
// Architectures.
@@ -47,7 +47,11 @@
// WebAssembly Processors supported.
//===----------------------------------------------------------------------===//
-def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>;
+// Minimal Viable Product.
+def : ProcessorModel<"mvp", NoSchedModel, []>;
+
+// Latest and greatest experimental version of WebAssembly. Bugs included!
+def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
//===----------------------------------------------------------------------===//
// Target Declaration