commit 03ca176ab32d3683086a7ba2bd64f550f2a81fd6
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jul 01 18:01:35 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jul 01 18:01:35 2019 +0000
tree c1147d2686091dbe58cf561c7f709212d4ffee62
parent 1023a2eca3f003c19532d5659f44bef169ab4519

GlobalISel: Verify G_MERGE_VALUES operand sizes

llvm-svn: 364822

llvm/lib/CodeGen/MachineVerifier.cpp

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 63fd05b..f9b5486 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1176,6 +1176,16 @@
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
     if (DstTy.isVector() || SrcTy.isVector())
       report("G_MERGE_VALUES cannot operate on vectors", MI);
+
+    const unsigned NumOps = MI->getNumOperands();
+    if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
+      report("G_MERGE_VALUES result size is inconsistent", MI);
+
+    for (unsigned I = 2; I != NumOps; ++I) {
+      if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
+        report("G_MERGE_VALUES source types do not match", MI);
+    }
+
     break;
   }
   case TargetOpcode::G_UNMERGE_VALUES: {