commit 03f419f3eb0c426a0a555be9abf7255a89b131cd
author Sander de Smalen <sander.desmalen@arm.com> Sun Apr 26 12:47:17 2020 +0100
committer Sander de Smalen <sander.desmalen@arm.com> Mon Apr 27 11:45:10 2020 +0100
tree e343ed4659bb5ae02923ac1dd62c0eca4c3bf152
parent b160e9e5394ca1f52a94b5f44c3610567b7bb420

[SveEmitter] IsInsertOp1SVALL and builtins for svqdec[bhwd] and svqinc[bhwd]

Some ACLE builtins leave out the argument to specify the predicate
pattern, which is expected to be expanded to an SV_ALL pattern.

This patch adds the flag IsInsertOp1SVALL to insert SV_ALL as the
second operand.

Reviewers: efriedma, SjoerdMeijer

Reviewed By: SjoerdMeijer

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78401

clang/utils/TableGen/SveEmitter.cpp

diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp
index 9a4b359..9376cd6 100644
--- a/clang/utils/TableGen/SveEmitter.cpp
+++ b/clang/utils/TableGen/SveEmitter.cpp
@@ -505,6 +505,7 @@
     Bitwidth = 16;
     ElementBitwidth = 1;
     break;
+  case 's':
   case 'a':
     Bitwidth = ElementBitwidth;
     NumVectors = 0;