commit 047473e293d926a4a87aa7cfbb670d828c70c5e6
author Akira Hatanaka <ahatanaka@mips.com> Wed Mar 28 00:24:17 2012 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Wed Mar 28 00:24:17 2012 +0000
tree 534c82b7aba4786116dc6eccd3eacf9c6d3a9f1a
parent 5ba593f50942273c77b40e754172be7e3e434705

Turn on post register allocation scheduler.

llvm-svn: 153554

llvm/lib/Target/Mips/MipsSubtarget.h

diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index ba0bbac..7faf77b 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -89,6 +89,9 @@
   InstrItineraryData InstrItins;
 
 public:
+  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+                                     AntiDepBreakMode& Mode,
+                                     RegClassVector& CriticalPathRCs) const;
 
   /// Only O32 and EABI supported right now.
   bool isABI_EABI() const { return MipsABI == EABI; }