Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.
llvm-svn: 116512
diff --git a/llvm/test/CodeGen/ARM/long_shift.ll b/llvm/test/CodeGen/ARM/long_shift.ll
index 43d58ec..4d2243a 100644
--- a/llvm/test/CodeGen/ARM/long_shift.ll
+++ b/llvm/test/CodeGen/ARM/long_shift.ll
@@ -3,7 +3,7 @@
define i64 @f0(i64 %A, i64 %B) {
; CHECK: f0
; CHECK: movs r3, r3, lsr #1
-; CHECK-NEXT: mov r2, r2, rrx
+; CHECK-NEXT: rrx r2, r2
; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbc r1, r1, r3
%tmp = bitcast i64 %A to i64