[ARM] Add missing pseudo-instruction for Thumb1 RSBS.
Shows up rarely for 64-bit arithmetic, more frequently for the compare
patterns added in r325323.
Differential Revision: https://reviews.llvm.org/D53848
llvm-svn: 345782
diff --git a/llvm/test/CodeGen/Thumb/branchless-cmp.ll b/llvm/test/CodeGen/Thumb/branchless-cmp.ll
index 8435529..ed34d63 100644
--- a/llvm/test/CodeGen/Thumb/branchless-cmp.ll
+++ b/llvm/test/CodeGen/Thumb/branchless-cmp.ll
@@ -20,8 +20,7 @@
; CHECK-LABEL: test1b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: adcs r0, r1
}
@@ -33,8 +32,7 @@
; CHECK-LABEL: test2a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: adcs r0, r1
}
@@ -71,8 +69,7 @@
; CHECK-LABEL: test3b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
-; CHECK-NEXT: movs r1, #0
-; CHECK-NEXT: subs r1, r1, r0
+; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: lsls r0, r1, #2
}
diff --git a/llvm/test/CodeGen/Thumb/long-setcc.ll b/llvm/test/CodeGen/Thumb/long-setcc.ll
index f077d0e..b8b9cff 100644
--- a/llvm/test/CodeGen/Thumb/long-setcc.ll
+++ b/llvm/test/CodeGen/Thumb/long-setcc.ll
@@ -9,8 +9,7 @@
define i1 @t2(i64 %x) {
; CHECK-LABEL: t2:
-; CHECK: movs r0, #0
-; CHECK: subs r0, r0, r1
+; CHECK: rsbs r0, r1, #0
; CHECK: adcs r0, r1
%tmp = icmp ult i64 %x, 4294967296
ret i1 %tmp