[WebAssembly] Update the br_if instructions' operand orders to match the spec.
llvm-svn: 260152
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
index fda9595..604e48c 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
@@ -16,12 +16,12 @@
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
// The condition operand is a boolean value which WebAssembly represents as i32.
-def BR_IF : I<(outs), (ins I32:$cond, bb_op:$dst),
+def BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
[(brcond I32:$cond, bb:$dst)],
- "br_if \t$cond, $dst">;
+ "br_if \t$dst, $cond">;
let isCodeGenOnly = 1 in
-def BR_UNLESS : I<(outs), (ins I32:$cond, bb_op:$dst), [],
- "br_unless\t$cond, $dst">;
+def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), [],
+ "br_unless\t$dst, $cond">;
let isBarrier = 1 in {
def BR : I<(outs), (ins bb_op:$dst),
[(br bb:$dst)],
@@ -32,9 +32,9 @@
} // Defs = [ARGUMENTS]
def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
- (BR_IF I32:$cond, bb_op:$dst)>;
+ (BR_IF bb_op:$dst, I32:$cond)>;
def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
- (BR_UNLESS I32:$cond, bb_op:$dst)>;
+ (BR_UNLESS bb_op:$dst, I32:$cond)>;
let Defs = [ARGUMENTS] in {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index a1181c8..ea8ffc9 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -107,22 +107,22 @@
if (HaveCond)
return true;
// If we're running after CFGStackify, we can't optimize further.
- if (!MI.getOperand(1).isMBB())
+ if (!MI.getOperand(0).isMBB())
return true;
Cond.push_back(MachineOperand::CreateImm(true));
- Cond.push_back(MI.getOperand(0));
- TBB = MI.getOperand(1).getMBB();
+ Cond.push_back(MI.getOperand(1));
+ TBB = MI.getOperand(0).getMBB();
HaveCond = true;
break;
case WebAssembly::BR_UNLESS:
if (HaveCond)
return true;
// If we're running after CFGStackify, we can't optimize further.
- if (!MI.getOperand(1).isMBB())
+ if (!MI.getOperand(0).isMBB())
return true;
Cond.push_back(MachineOperand::CreateImm(false));
- Cond.push_back(MI.getOperand(0));
- TBB = MI.getOperand(1).getMBB();
+ Cond.push_back(MI.getOperand(1));
+ TBB = MI.getOperand(0).getMBB();
HaveCond = true;
break;
case WebAssembly::BR:
@@ -177,11 +177,11 @@
assert(Cond.size() == 2 && "Expected a flag and a successor block");
if (Cond[0].getImm()) {
- BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addOperand(Cond[1]).addMBB(TBB);
+ BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[1]);
} else {
BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
- .addOperand(Cond[1])
- .addMBB(TBB);
+ .addMBB(TBB)
+ .addOperand(Cond[1]);
}
if (!FBB)
return 1;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
index 23a3b4d..201c5ab 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
@@ -66,7 +66,7 @@
if (MI->getOpcode() != WebAssembly::BR_UNLESS)
continue;
- unsigned Cond = MI->getOperand(0).getReg();
+ unsigned Cond = MI->getOperand(1).getReg();
bool Inverted = false;
// Attempt to invert the condition in place.
@@ -124,8 +124,8 @@
// delete the br_unless.
assert(Inverted);
BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
- .addReg(Cond)
- .addOperand(MI->getOperand(1));
+ .addOperand(MI->getOperand(0))
+ .addReg(Cond);
MBB.erase(MI);
}
}