commit 06d783765a0740dbb486da4d2d2928442f065fe5
author Craig Topper <craig.topper@intel.com> Wed Mar 21 19:30:30 2018 +0000
committer Craig Topper <craig.topper@intel.com> Wed Mar 21 19:30:30 2018 +0000
tree c3fa3c7c1eab2fa694520583b65022881fb41cc7
parent 2854dc93e1efe3086f55ca187284de53149b860e

[TableGen] Use count_if instead of a manual loop. NFC

llvm-svn: 328137

llvm/utils/TableGen/CodeGenSchedule.cpp

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 0cdd7d2..9b419d1 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -759,11 +759,10 @@
       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
       if (!RWDefs.empty()) {
         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
-        unsigned OrigNumInstrs = 0;
-        for (Record *OIDef : *OrigInstDefs) {
-          if (InstrClassMap[OIDef] == OldSCIdx)
-            ++OrigNumInstrs;
-        }
+        unsigned OrigNumInstrs =
+          count_if(*OrigInstDefs, [&](Record *OIDef) {
+                     return InstrClassMap[OIDef] == OldSCIdx;
+                   });
         if (OrigNumInstrs == InstDefs.size()) {
           assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
                  "expected a generic SchedClass");