[PowerPC] Add profitablilty check for conversion to mtctr loops
Add profitability checks for modifying counted loops to use the mtctr instruction.
The latency of mtctr is only justified if there are more than 4 comparisons that
will be removed as a result. Usually counted loops are formed relatively early
and before unrolling, so most low trip count loops often don't survive. However
we want to ensure that if they do, we do not mistakenly update them to mtctr loops.
Use CodeMetrics to ensure we are only doing this for small loops with small trip counts.
Differential Revision: https://reviews.llvm.org/D38212
llvm-svn: 315592
diff --git a/llvm/test/CodeGen/PowerPC/ctr-minmaxnum.ll b/llvm/test/CodeGen/PowerPC/ctr-minmaxnum.ll
index 2b0a7cc..e38f851 100644
--- a/llvm/test/CodeGen/PowerPC/ctr-minmaxnum.ll
+++ b/llvm/test/CodeGen/PowerPC/ctr-minmaxnum.ll
@@ -1,6 +1,5 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=a2q < %s | FileCheck %s --check-prefix=QPX
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -mcpu=a2q < %s | FileCheck %s --check-prefix=QPX
declare float @fabsf(float)
@@ -38,6 +37,9 @@
; CHECK-LABEL: test1:
; CHECK-NOT: mtctr
; CHECK: bl fminf
+; CHECK-NOT: bl fminf
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test1v(<4 x float> %f, <4 x float>* %fp) {
entry:
@@ -48,7 +50,7 @@
%0 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %f, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
store <4 x float> %0, <4 x float>* %fp, align 16
%1 = add i64 %invar_address.dim.0.01, 1
- %2 = icmp eq i64 %1, 2
+ %2 = icmp eq i64 %1, 4
br i1 %2, label %loop_exit, label %loop_body
loop_exit:
@@ -56,8 +58,15 @@
}
; CHECK-LABEL: test1v:
+; CHECK: bl fminf
; CHECK-NOT: mtctr
; CHECK: bl fminf
+; CHECK-NOT: mtctr
+; CHECK: bl fminf
+; CHECK-NOT: mtctr
+; CHECK: bl fminf
+; CHECK-NOT: bl fminf
+; CHECK: blr
; QPX-LABEL: test1v:
; QPX: mtctr
@@ -83,6 +92,9 @@
; CHECK-LABEL: test1a:
; CHECK-NOT: mtctr
; CHECK: bl fminf
+; CHECK-NOT: bl fminf
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test2(float %f, float* %fp) {
entry:
@@ -103,6 +115,9 @@
; CHECK-LABEL: test2:
; CHECK-NOT: mtctr
; CHECK: bl fmaxf
+; CHECK-NOT: bl fmaxf
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test2v(<4 x double> %f, <4 x double>* %fp) {
entry:
@@ -113,7 +128,7 @@
%0 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %f, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>)
store <4 x double> %0, <4 x double>* %fp, align 16
%1 = add i64 %invar_address.dim.0.01, 1
- %2 = icmp eq i64 %1, 2
+ %2 = icmp eq i64 %1, 4
br i1 %2, label %loop_exit, label %loop_body
loop_exit:
@@ -121,8 +136,15 @@
}
; CHECK-LABEL: test2v:
+; CHECK: bl fmax
; CHECK-NOT: mtctr
; CHECK: bl fmax
+; CHECK-NOT: mtctr
+; CHECK: bl fmax
+; CHECK-NOT: mtctr
+; CHECK: bl fmax
+; CHECK-NOT: bl fmax
+; CHECK: blr
; QPX-LABEL: test2v:
; QPX: mtctr
@@ -148,6 +170,9 @@
; CHECK-LABEL: test2a:
; CHECK-NOT: mtctr
; CHECK: bl fmaxf
+; CHECK-NOT: bl fmaxf
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test3(double %f, double* %fp) {
entry:
@@ -168,6 +193,9 @@
; CHECK-LABEL: test3:
; CHECK-NOT: mtctr
; CHECK: bl fmin
+; CHECK-NOT: bl fmin
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test3a(double %f, double* %fp) {
entry:
@@ -188,6 +216,9 @@
; CHECK-LABEL: test3a:
; CHECK-NOT: mtctr
; CHECK: bl fmin
+; CHECK-NOT: bl fmin
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test4(double %f, double* %fp) {
entry:
@@ -208,6 +239,9 @@
; CHECK-LABEL: test4:
; CHECK-NOT: mtctr
; CHECK: bl fmax
+; CHECK-NOT: bl fmax
+; CHECK-NOT: mtctr
+; CHECK: blr
define void @test4a(double %f, double* %fp) {
entry:
@@ -228,4 +262,7 @@
; CHECK-LABEL: test4a:
; CHECK-NOT: mtctr
; CHECK: bl fmax
+; CHECK-NOT: bl fmax
+; CHECK-NOT: mtctr
+; CHECK: blr