Make prevectorization width configurable
Polly uses 'prevectorization' to enable outer loop vectorization. When
vectorizing an outer loop, we strip-mine <number-of-prevec-dims> loop
iterations which are than interchanged to the innermost level such that LLVM's
inner loop vectorizer (or Polly's simple vectorizer) can easily vectorize this
loop. The number of loop iterations to strip-mine is now configurable with the
option -polly-prevect-width=<number-of-prevec-dims>.
This is mostly a debugging option. We should probably add a heuristic that
derives the number of prevectorization dimensions from the target data and
the data types used.
llvm-svn: 245424
diff --git a/polly/lib/Transform/ScheduleOptimizer.cpp b/polly/lib/Transform/ScheduleOptimizer.cpp
index 9a54c1d..7ff8e7c 100644
--- a/polly/lib/Transform/ScheduleOptimizer.cpp
+++ b/polly/lib/Transform/ScheduleOptimizer.cpp
@@ -107,6 +107,12 @@
cl::desc("Maximize the band depth (yes/no)"), cl::Hidden,
cl::init("yes"), cl::ZeroOrMore, cl::cat(PollyCategory));
+static cl::opt<int> PrevectorWidth(
+ "polly-prevect-width",
+ cl::desc(
+ "The number of loop iterations to strip-mine for pre-vectorization"),
+ cl::Hidden, cl::init(4), cl::ZeroOrMore, cl::cat(PollyCategory));
+
static cl::opt<int> DefaultTileSize(
"polly-default-tile-size",
cl::desc("The default tile size (if not enough were provided by"
@@ -176,7 +182,7 @@
/// reason about parallelism.
static __isl_give isl_schedule_node *
prevectSchedBand(__isl_take isl_schedule_node *Node, unsigned DimToVectorize,
- int VectorWidth = 4);
+ int VectorWidth);
/// @brief Apply additional optimizations on the bands in the schedule tree.
///
@@ -298,7 +304,7 @@
for (int i = Dims - 1; i >= 0; i--)
if (isl_schedule_node_band_member_get_coincident(Node, i)) {
- Node = IslScheduleOptimizer::prevectSchedBand(Node, i);
+ Node = IslScheduleOptimizer::prevectSchedBand(Node, i, PrevectorWidth);
break;
}