commit 0863c161e9431eec93c6c6e318748019dfb4fed2
author Ruchira Sasanka <sasanka@students.uiuc.edu> Wed Oct 24 22:05:34 2001 +0000
committer Ruchira Sasanka <sasanka@students.uiuc.edu> Wed Oct 24 22:05:34 2001 +0000
tree ac401a0d38ee7aed9edcef1956abc7665a4a26b0
parent f9e623e1f9e4f5df3184772d5bd194664ae06832

Fixed load syntax in EmitAssembly
Fixed cpReg2Mem (store) operand oreder in SparcRegInfo.cpp

llvm-svn: 984

llvm/lib/Target/Sparc/EmitAssembly.cpp

diff --git a/llvm/lib/Target/Sparc/EmitAssembly.cpp b/llvm/lib/Target/Sparc/EmitAssembly.cpp
index aadc790..59cd52a 100644
--- a/llvm/lib/Target/Sparc/EmitAssembly.cpp
+++ b/llvm/lib/Target/Sparc/EmitAssembly.cpp
@@ -182,10 +182,47 @@
     printOperand(MI->getOperand(1));
     Out << endl;
     return;
-    
+
   default: break;
   }
 
+  if( Target.getInstrInfo().isLoad(Opcode) ) {  // if Load
+    assert(MI->getNumOperands() == 3 && "Loads must have 3 operands");
+    Out << "[";
+    printOperand(MI->getOperand(0));
+
+    const MachineOperand& ImmOp = MI->getOperand(1);
+    if( ImmOp.getImmedValue() >= 0)
+      Out << "+";
+    printOperand(ImmOp);
+    Out << "]"; 
+    Out << ", ";
+
+    printOperand(MI->getOperand(2));
+    Out << endl;
+    return;
+
+  }
+
+  if( Target.getInstrInfo().isStore(Opcode) ) {  // if Store
+    assert(MI->getNumOperands() == 3 && "Stores must have 3 operands");
+    printOperand(MI->getOperand(0));
+    Out << ", ";
+    Out << "[";
+    printOperand(MI->getOperand(1));
+
+    const MachineOperand& ImmOp = MI->getOperand(2);
+    if( ImmOp.getImmedValue() >= 0)
+      Out << "+";
+    printOperand(ImmOp);
+    Out << "]"; 
+    Out << endl;
+    return;
+
+  }
+
+
+
   unsigned Mask = getOperandMask(Opcode);
 
   bool NeedComma = false;

llvm/lib/Target/Sparc/SparcRegInfo.cpp

diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
index 54cfb3c..dfb5517 100644
--- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
@@ -775,8 +775,8 @@
 
 
 //---------------------------------------------------------------------------
-// Copy from a register to memory. Register number must be the unified
-// register number
+// Copy from a register to memory (i.e., Store). Register number must 
+// be the unified register number
 //---------------------------------------------------------------------------
 
 
@@ -794,24 +794,24 @@
   case IntCCRegType:
   case FloatCCRegType: 
     MI = new MachineInstr(STX, 3);
-    MI->SetMachineOperand(0, DestPtrReg, false);
-    MI->SetMachineOperand(1, SrcReg, false);
+    MI->SetMachineOperand(0, SrcReg, false);
+    MI->SetMachineOperand(1, DestPtrReg, false);
     MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, 
 			  (int64_t) Offset, false);
     break;
 
   case FPSingleRegType:
     MI = new MachineInstr(ST, 3);
-    MI->SetMachineOperand(0, DestPtrReg, false);
-    MI->SetMachineOperand(1, SrcReg, false);
+    MI->SetMachineOperand(0, SrcReg, false);
+    MI->SetMachineOperand(1, DestPtrReg, false);
     MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, 
 			  (int64_t) Offset, false);
     break;
 
   case FPDoubleRegType:
     MI = new MachineInstr(STD, 3);
-    MI->SetMachineOperand(0, DestPtrReg, false);
-    MI->SetMachineOperand(1, SrcReg, false);
+    MI->SetMachineOperand(0, SrcReg, false);
+    MI->SetMachineOperand(1, DestPtrReg, false);
     MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, 
 			  (int64_t) Offset, false);
     break;
@@ -825,7 +825,7 @@
 
 
 //---------------------------------------------------------------------------
-// Copy from memory to a reg. Register number must be the unified
+// Copy from memory to a reg (i.e., Load) Register number must be the unified
 // register number
 //---------------------------------------------------------------------------