Added emulation of shifts to the IR interpreter.
<rdar://problem/12978619>
llvm-svn: 172013
diff --git a/lldb/source/Expression/IRInterpreter.cpp b/lldb/source/Expression/IRInterpreter.cpp
index f39d135..2027556 100644
--- a/lldb/source/Expression/IRInterpreter.cpp
+++ b/lldb/source/Expression/IRInterpreter.cpp
@@ -1042,17 +1042,23 @@
}
}
break;
+ case Instruction::And:
+ case Instruction::AShr:
case Instruction::IntToPtr:
case Instruction::PtrToInt:
case Instruction::Load:
+ case Instruction::LShr:
case Instruction::Mul:
+ case Instruction::Or:
case Instruction::Ret:
case Instruction::SDiv:
+ case Instruction::Shl:
case Instruction::SRem:
case Instruction::Store:
case Instruction::Sub:
case Instruction::UDiv:
case Instruction::URem:
+ case Instruction::Xor:
case Instruction::ZExt:
break;
}
@@ -1139,6 +1145,12 @@
case Instruction::UDiv:
case Instruction::SRem:
case Instruction::URem:
+ case Instruction::Shl:
+ case Instruction::LShr:
+ case Instruction::AShr:
+ case Instruction::And:
+ case Instruction::Or:
+ case Instruction::Xor:
{
const BinaryOperator *bin_op = dyn_cast<BinaryOperator>(inst);
@@ -1202,6 +1214,25 @@
case Instruction::URem:
result = L.GetRawBits64(0) % R.GetRawBits64(1);
break;
+ case Instruction::Shl:
+ result = L << R;
+ break;
+ case Instruction::AShr:
+ result = L >> R;
+ break;
+ case Instruction::LShr:
+ result = L;
+ result.ShiftRightLogical(R);
+ break;
+ case Instruction::And:
+ result = L & R;
+ break;
+ case Instruction::Or:
+ result = L | R;
+ break;
+ case Instruction::Xor:
+ result = L ^ R;
+ break;
}
frame.AssignValue(inst, result, llvm_module);