commit 0994bd57fb014d5916d1aa5a914ce4e681365adb
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 01 00:56:27 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jul 01 00:56:27 2016 +0000
tree 8a0af523fa37345d94fc7273258a21386754e57e
parent 286d94884b87c4f237fdeb57be696f0b52b5c6a5

AMDGPU: Implement getLoadStoreVecRegBitWidth

llvm-svn: 274312

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index ea4f582..d7efaa5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -82,6 +82,7 @@
 
   unsigned getNumberOfRegisters(bool Vector);
   unsigned getRegisterBitWidth(bool Vector);
+  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace);
   unsigned getMaxInterleaveFactor(unsigned VF);
 
   int getArithmeticInstrCost(