AMDGPU: Refactor MIMG instruction TableGen using generic tables
Summary:
This allows us to access rich information about MIMG opcodes from C++ code.
Simplifying the mapping between equivalent opcodes of different data size
becomes quite natural.
This also flattens the MIMG-related class and multiclass hierarchy a little,
and collapses together some of the scaffolding for sample and gather4 opcodes.
Change-Id: I1a2549fdc1e881ff100e5393d2d87e73729a0ccd
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48016
llvm-svn: 335227
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 741cf0e..d7908f6 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -329,19 +329,15 @@
int NewOpcode = -1;
- if (IsAtomic) {
- if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) {
- NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), DstSize);
- }
- if (NewOpcode == -1) return MCDisassembler::Success;
- } else if (IsGather4) {
+ if (IsGather4) {
if (D16 && AMDGPU::hasPackedD16(STI))
- NewOpcode = AMDGPU::getMIMGGatherOpPackedD16(MI.getOpcode());
+ NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), 2);
else
return MCDisassembler::Success;
} else {
- NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), DstSize);
- assert(NewOpcode != -1 && "could not find matching mimg channel instruction");
+ NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), DstSize);
+ if (NewOpcode == -1)
+ return MCDisassembler::Success;
}
auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;