commit 0b7e4cd107e81db6bac9dc6747df28e8a44a6e66
author Chris Lattner <sabre@nondot.org> Sat Apr 02 05:03:24 2005 +0000
committer Chris Lattner <sabre@nondot.org> Sat Apr 02 05:03:24 2005 +0000
tree faaf4c15cdbd14e5b0dc1b6bc5d8326ce3d2dbba
parent 13fe99c807fd4bf0d0571b47ab08ec03e872044b

This target doesn't support fabs/fneg yet.

llvm-svn: 21010

llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp

diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index a6ebbad..751b553 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -53,6 +53,10 @@
       // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
       setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
       setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
+
+      // We don't support these yet.
+      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
+      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
       
       addLegalFPImmediate(+0.0); // Necessary for FSEL
       addLegalFPImmediate(-0.0); //