commit 0ba797e8f7f02fcced18759e0fd912728bb38c2e
author Kristof Beyls <kristof.beyls@arm.com> Fri Feb 22 10:01:33 2013 +0000
committer Kristof Beyls <kristof.beyls@arm.com> Fri Feb 22 10:01:33 2013 +0000
tree 06ee390fc53702b9850cdafc40aedd26264b0a48
parent 3065014026db868bfcd76adef7247319ea96e0b2

Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.

The Printer will now print instructions with the correct alignment specifier syntax, like
    vld1.8  {d16}, [r0:64]

llvm-svn: 175884

llvm/test/CodeGen/ARM/reg_sequence.ll

diff --git a/llvm/test/CodeGen/ARM/reg_sequence.ll b/llvm/test/CodeGen/ARM/reg_sequence.ll
index 6d6586e..fd2083c 100644
--- a/llvm/test/CodeGen/ARM/reg_sequence.ll
+++ b/llvm/test/CodeGen/ARM/reg_sequence.ll
@@ -242,8 +242,8 @@
 ; CHECK:        vldr
 ; CHECK-NOT:    vmov d{{.*}}, d16
 ; CHECK:        vmov.i32 d17
-; CHECK-NEXT:   vst1.64 {d16, d17}, [r0, :128]
-; CHECK-NEXT:   vst1.64 {d16, d17}, [r0, :128]
+; CHECK-NEXT:   vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT:   vst1.64 {d16, d17}, [r0:128]
   %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
   %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
   store <4 x float> %4, <4 x float>* undef, align 16