Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 444f618..18fcee6 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -232,7 +232,7 @@
if (!MO.isReg() || !MO.isImplicit())
return false;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0)
return false;
@@ -252,7 +252,7 @@
if (!MO.isReg()) continue;
if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
IsImplicitDefUse(MI, MO)) {
- const unsigned Reg = MO.getReg();
+ const Register Reg = MO.getReg();
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
PassthruRegs.insert(*SubRegs);
@@ -365,7 +365,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
@@ -375,7 +375,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
@@ -418,7 +418,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
// Ignore KILLs and passthru registers for liveness...
if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
@@ -471,7 +471,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
@@ -506,7 +506,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
if (FirstReg != 0) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index cc15669..2daad1f 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -783,7 +783,7 @@
/// emitImplicitDef - This method emits the specified machine instruction
/// that is an implicit def.
void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
- unsigned RegNo = MI->getOperand(0).getReg();
+ Register RegNo = MI->getOperand(0).getReg();
SmallString<128> Str;
raw_svector_ostream OS(Str);
diff --git a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
index cc5effc..9d05cfe 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
@@ -177,13 +177,13 @@
IndicesToErase.push_back(Index);
Entry.endEntry(NewIndex);
}
- if (unsigned Reg = isDescribedByReg(DV))
+ if (Register Reg = isDescribedByReg(DV))
TrackedRegs[Reg] |= !Overlaps;
}
// If the new debug value is described by a register, add tracking of
// that register if it is not already tracked.
- if (unsigned NewReg = isDescribedByReg(DV)) {
+ if (Register NewReg = isDescribedByReg(DV)) {
if (!TrackedRegs.count(NewReg))
addRegDescribedVar(RegVars, NewReg, Var);
LiveEntries[Var].insert(NewIndex);
@@ -234,7 +234,7 @@
DbgLabelInstrMap &DbgLabels) {
const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
- unsigned FrameReg = TRI->getFrameRegister(*MF);
+ Register FrameReg = TRI->getFrameRegister(*MF);
RegDescribedVarsMap RegVars;
DbgValueEntriesMap LiveEntries;
for (const auto &MBB : *MF) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index 364119a..136c0e9 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -660,9 +660,9 @@
DbgValueLoc DbgLocVal(ParamValue->second, Val);
finishCallSiteParam(DbgLocVal, Reg);
} else if (ParamValue->first->isReg()) {
- unsigned RegLoc = ParamValue->first->getReg();
+ Register RegLoc = ParamValue->first->getReg();
unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
- unsigned FP = TRI->getFrameRegister(*MF);
+ Register FP = TRI->getFrameRegister(*MF);
bool IsSPorFP = (RegLoc == SP) || (RegLoc == FP);
if (TRI->isCalleeSavedPhysReg(RegLoc, *MF) || IsSPorFP) {
DbgValueLoc DbgLocVal(ParamValue->second,
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index ecd6ac4..a0a072b 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -1871,7 +1871,7 @@
for (const MachineOperand &MO : Loc->operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isUse()) {
@@ -1909,7 +1909,7 @@
return Loc;
if (!MO.isReg() || MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (Uses.count(Reg)) {
@@ -1937,7 +1937,7 @@
for (const MachineOperand &MO : PI->operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isUse()) {
@@ -2010,7 +2010,7 @@
}
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isDef()) {
@@ -2060,7 +2060,7 @@
for (const MachineOperand &MO : TIB->operands()) {
if (!MO.isReg() || !MO.isUse() || !MO.isKill())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (!AllDefsSet.count(Reg)) {
@@ -2078,7 +2078,7 @@
for (const MachineOperand &MO : TIB->operands()) {
if (!MO.isReg() || !MO.isDef() || MO.isDead())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || Register::isVirtualRegister(Reg))
continue;
addRegAndItsAliases(Reg, TRI, ActiveDefsSet);
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index cc4b2ca..a65b344 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -109,7 +109,7 @@
MachineOperand &MO = MI->getOperand(OpIdx);
assert(MO.isUndef() && "Expected undef machine operand");
- unsigned OriginalReg = MO.getReg();
+ Register OriginalReg = MO.getReg();
// Update only undef operands that have reg units that are mapped to one root.
for (MCRegUnitIterator Unit(OriginalReg, TRI); Unit.isValid(); ++Unit) {
@@ -162,7 +162,7 @@
bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
unsigned Pref) {
- unsigned reg = MI->getOperand(OpIdx).getReg();
+ Register reg = MI->getOperand(OpIdx).getReg();
unsigned Clearance = RDA->getClearance(MI, reg);
LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp
index 6d0a02f..bf97aae 100644
--- a/llvm/lib/CodeGen/CalcSpillWeights.cpp
+++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp
@@ -244,7 +244,7 @@
// Get allocation hints from copies.
if (!mi->isCopy())
continue;
- unsigned hint = copyHint(mi, li.reg, tri, mri);
+ Register hint = copyHint(mi, li.reg, tri, mri);
if (!hint)
continue;
// Force hweight onto the stack so that x86 doesn't add hidden precision,
diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
index 4144c24..22575d5 100644
--- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@@ -187,7 +187,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
const TargetRegisterClass *NewRC = nullptr;
@@ -272,7 +272,7 @@
}
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
if (!MO.isDef()) continue;
@@ -303,7 +303,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
if (!MO.isUse()) continue;
@@ -612,7 +612,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
AntiDepReg = 0;
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index 4fe1112..9a537c8 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -75,7 +75,7 @@
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDef()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg)) {
// Don't delete live physreg defs, or any reserved register defs.
if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
@@ -140,7 +140,7 @@
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDef()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg)) {
// Check the subreg set, not the alias set, because a def
// of a super-register may still be partially live after
@@ -159,7 +159,7 @@
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isUse()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg)) {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
LivePhysRegs.set(*AI);
diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
index 31dea09..6d5306c 100644
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -154,7 +154,7 @@
const TargetRegisterClass *DstRC,
const MachineOperand &MO) {
assert(lowersToCopies(MI));
- unsigned SrcReg = MO.getReg();
+ Register SrcReg = MO.getReg();
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
if (DstRC == SrcRC)
return false;
@@ -194,7 +194,7 @@
LaneBitmask UsedLanes) {
if (!MO.readsReg())
return;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!Register::isVirtualRegister(MOReg))
return;
@@ -250,7 +250,7 @@
return MO2UsedLanes;
const MachineOperand &Def = MI.getOperand(0);
- unsigned DefReg = Def.getReg();
+ Register DefReg = Def.getReg();
const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
LaneBitmask MO1UsedLanes;
if (RC->CoveredBySubRegs)
@@ -285,7 +285,7 @@
if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
return;
const MachineOperand &Def = *MI.defs().begin();
- unsigned DefReg = Def.getReg();
+ Register DefReg = Def.getReg();
if (!Register::isVirtualRegister(DefReg))
return;
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
@@ -377,7 +377,7 @@
for (const MachineOperand &MO : DefMI.uses()) {
if (!MO.isReg() || !MO.readsReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg)
continue;
@@ -428,7 +428,7 @@
if (lowersToCopies(UseMI)) {
assert(UseMI.getDesc().getNumDefs() == 1);
const MachineOperand &Def = *UseMI.defs().begin();
- unsigned DefReg = Def.getReg();
+ Register DefReg = Def.getReg();
// The used lanes of COPY-like instruction operands are determined by the
// following dataflow analysis.
if (Register::isVirtualRegister(DefReg)) {
@@ -470,7 +470,7 @@
if (!lowersToCopies(MI))
return false;
const MachineOperand &Def = MI.getOperand(0);
- unsigned DefReg = Def.getReg();
+ Register DefReg = Def.getReg();
if (!Register::isVirtualRegister(DefReg))
return false;
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
@@ -482,7 +482,7 @@
if (UsedLanes.any())
return false;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (Register::isVirtualRegister(MOReg)) {
const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
*CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
@@ -536,7 +536,7 @@
for (MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
unsigned RegIdx = Register::virtReg2Index(Reg);
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 00a5ce2..61e994e 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -232,7 +232,7 @@
}
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// Remember clobbered regunits.
if (MO.isDef() && Register::isPhysicalRegister(Reg))
@@ -288,7 +288,7 @@
// We're ignoring regmask operands. That is conservatively correct.
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
// I clobbers Reg, so it isn't live before I.
@@ -467,7 +467,7 @@
for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
PHIInfo &PI = PHIs[i];
LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
- unsigned DstReg = PI.PHI->getOperand(0).getReg();
+ Register DstReg = PI.PHI->getOperand(0).getReg();
TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
PI.PHI->eraseFromParent();
@@ -494,7 +494,7 @@
// equal.
DstReg = PI.TReg;
} else {
- unsigned PHIDst = PI.PHI->getOperand(0).getReg();
+ Register PHIDst = PI.PHI->getOperand(0).getReg();
DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
TII->insertSelect(*Head, FirstTerm, HeadDL,
DstReg, Cond, PI.TReg, PI.FReg);
diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
index 381cefe..1fc57fa 100644
--- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
+++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
@@ -79,13 +79,13 @@
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
- unsigned DstReg = MI->getOperand(0).getReg();
- unsigned InsReg = MI->getOperand(2).getReg();
+ Register DstReg = MI->getOperand(0).getReg();
+ Register InsReg = MI->getOperand(2).getReg();
assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
unsigned SubIdx = MI->getOperand(3).getImm();
assert(SubIdx != 0 && "Invalid index for insert_subreg");
- unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
+ Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
assert(Register::isPhysicalRegister(DstReg) &&
"Insert destination must be in a physical register");
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index 7893905..9f81b0a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -332,7 +332,7 @@
const GISelInstProfileBuilder &GISelInstProfileBuilder::addNodeIDMachineOperand(
const MachineOperand &MO) const {
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!MO.isDef())
addNodeIDRegNum(Reg);
LLT Ty = MRI.getType(Reg);
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 18ea45e..b1bf825 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -62,8 +62,8 @@
bool CombinerHelper::matchCombineCopy(MachineInstr &MI) {
if (MI.getOpcode() != TargetOpcode::COPY)
return false;
- unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
LLT DstTy = MRI.getType(DstReg);
LLT SrcTy = MRI.getType(SrcReg);
// Simple Copy Propagation.
@@ -73,8 +73,8 @@
return false;
}
void CombinerHelper::applyCombineCopy(MachineInstr &MI) {
- unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
MI.eraseFromParent();
replaceRegWith(MRI, DstReg, SrcReg);
}
@@ -286,7 +286,7 @@
// up the type and extend so that it uses the preferred use.
if (UseMI->getOpcode() == Preferred.ExtendOpcode ||
UseMI->getOpcode() == TargetOpcode::G_ANYEXT) {
- unsigned UseDstReg = UseMI->getOperand(0).getReg();
+ Register UseDstReg = UseMI->getOperand(0).getReg();
MachineOperand &UseSrcMO = UseMI->getOperand(1);
const LLT &UseDstTy = MRI.getType(UseDstReg);
if (UseDstReg != ChosenDstReg) {
@@ -883,8 +883,8 @@
unsigned DstAlign = MemOp->getBaseAlignment();
unsigned SrcAlign = 0;
- unsigned Dst = MI.getOperand(1).getReg();
- unsigned Src = MI.getOperand(2).getReg();
+ Register Dst = MI.getOperand(1).getReg();
+ Register Src = MI.getOperand(2).getReg();
Register Len = MI.getOperand(3).getReg();
if (ID != Intrinsic::memset) {
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index 517f13c..d699b4d 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -160,8 +160,8 @@
--MII;
if (MI.getOpcode() != TargetOpcode::COPY)
continue;
- unsigned SrcReg = MI.getOperand(1).getReg();
- unsigned DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
if (Register::isVirtualRegister(SrcReg) &&
Register::isVirtualRegister(DstReg)) {
auto SrcRC = MRI.getRegClass(SrcReg);
diff --git a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
index 3592409..8dd9969 100644
--- a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
@@ -79,7 +79,7 @@
return true;
case TargetOpcode::G_GLOBAL_VALUE: {
unsigned RematCost = TTI->getGISelRematGlobalCost();
- unsigned Reg = MI.getOperand(0).getReg();
+ Register Reg = MI.getOperand(0).getReg();
unsigned MaxUses = maxUses(RematCost);
if (MaxUses == UINT_MAX)
return true; // Remats are "free" so always localize.
@@ -121,7 +121,7 @@
LLVM_DEBUG(dbgs() << "Should localize: " << MI);
assert(MI.getDesc().getNumDefs() == 1 &&
"More than one definition not supported yet");
- unsigned Reg = MI.getOperand(0).getReg();
+ Register Reg = MI.getOperand(0).getReg();
// Check if all the users of MI are local.
// We are going to invalidation the list of use operands, so we
// can't use range iterator.
@@ -151,7 +151,7 @@
LocalizedMI);
// Set a new register for the definition.
- unsigned NewReg = MRI->createGenericVirtualRegister(MRI->getType(Reg));
+ Register NewReg = MRI->createGenericVirtualRegister(MRI->getType(Reg));
MRI->setRegClassOrRegBank(NewReg, MRI->getRegClassOrRegBank(Reg));
LocalizedMI->getOperand(0).setReg(NewReg);
NewVRegIt =
@@ -177,7 +177,7 @@
// many users, but this case may be better served by regalloc improvements.
for (MachineInstr *MI : LocalizedInstrs) {
- unsigned Reg = MI->getOperand(0).getReg();
+ Register Reg = MI->getOperand(0).getReg();
MachineBasicBlock &MBB = *MI->getParent();
// All of the user MIs of this reg.
SmallPtrSet<MachineInstr *, 32> Users;
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 907cb67..be09db1 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -43,7 +43,7 @@
const RegisterBankInfo &RBI, MachineInstr &InsertPt,
const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
unsigned OpIdx) {
- unsigned Reg = RegMO.getReg();
+ Register Reg = RegMO.getReg();
// Assume physical registers are properly constrained.
assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
@@ -72,7 +72,7 @@
MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
const MachineOperand &RegMO, unsigned OpIdx) {
- unsigned Reg = RegMO.getReg();
+ Register Reg = RegMO.getReg();
// Assume physical registers are properly constrained.
assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
@@ -128,7 +128,7 @@
LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
assert(MO.isReg() && "Unsupported non-reg operand");
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// Physical registers don't need to be constrained.
if (Register::isPhysicalRegister(Reg))
continue;
@@ -168,7 +168,7 @@
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg))
return false;
}
@@ -288,7 +288,7 @@
if (!DstTy.isValid())
return nullptr;
while (DefMI->getOpcode() == TargetOpcode::COPY) {
- unsigned SrcReg = DefMI->getOperand(1).getReg();
+ Register SrcReg = DefMI->getOperand(1).getReg();
auto SrcTy = MRI.getType(SrcReg);
if (!SrcTy.isValid() || SrcTy != DstTy)
break;
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index 6f6581e..8331719 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -1815,7 +1815,7 @@
for (const MachineOperand &MO : FI.operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isDef()) {
@@ -1983,7 +1983,7 @@
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isDef() && !LaterRedefs.count(Reg))
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
index 1e82ea6..b7dcaec 100644
--- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp
+++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
@@ -278,12 +278,12 @@
if (!(MOA.isReg() && MOA.getReg()))
continue;
- unsigned RegA = MOA.getReg();
+ Register RegA = MOA.getReg();
for (auto MOB : B->operands()) {
if (!(MOB.isReg() && MOB.getReg()))
continue;
- unsigned RegB = MOB.getReg();
+ Register RegB = MOB.getReg();
if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
return false;
@@ -517,7 +517,7 @@
//
// we must ensure that there are no instructions between the 'test' and
// conditional jump that modify %rax.
- const unsigned PointerReg = MBP.LHS.getReg();
+ const Register PointerReg = MBP.LHS.getReg();
assert(MBP.ConditionDef->getParent() == &MBB && "Should be in basic block");
@@ -689,7 +689,7 @@
for (const MachineOperand &MO : FaultingInstr->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || MBB->isLiveIn(Reg))
continue;
MBB->addLiveIn(Reg);
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 7fb3fff..0a10f91 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -376,7 +376,7 @@
assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
#endif
- unsigned SrcReg = CopyMI.getOperand(1).getReg();
+ Register SrcReg = CopyMI.getOperand(1).getReg();
LiveInterval &SrcLI = LIS.getInterval(SrcReg);
VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
LiveQueryResult SrcQ = SrcLI.Query(Idx);
@@ -844,7 +844,7 @@
for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
if (!MO->isReg())
continue;
- unsigned Reg = MO->getReg();
+ Register Reg = MO->getReg();
if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) {
continue;
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp
index 82231a0..b82cef9 100644
--- a/llvm/lib/CodeGen/LiveDebugValues.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues.cpp
@@ -898,8 +898,8 @@
return false;
};
- unsigned SrcReg = SrcRegOp->getReg();
- unsigned DestReg = DestRegOp->getReg();
+ Register SrcReg = SrcRegOp->getReg();
+ Register DestReg = DestRegOp->getReg();
// We want to recognize instructions where destination register is callee
// saved register. If register that could be clobbered by the call is
@@ -1182,7 +1182,7 @@
const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
- unsigned FP = TRI->getFrameRegister(MF);
+ Register FP = TRI->getFrameRegister(MF);
auto IsRegOtherThanSPAndFP = [&](const MachineOperand &Op) -> bool {
return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
};
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 6ba8c48..31b38c1 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -607,7 +607,7 @@
bool Discard = false;
if (MI.getOperand(0).isReg() &&
Register::isVirtualRegister(MI.getOperand(0).getReg())) {
- const unsigned Reg = MI.getOperand(0).getReg();
+ const Register Reg = MI.getOperand(0).getReg();
if (!LIS->hasInterval(Reg)) {
// The DBG_VALUE is described by a virtual register that does not have a
// live interval. Discard the DBG_VALUE.
@@ -768,7 +768,7 @@
// Copies of the full value.
if (MO.getSubReg() || !MI->isCopy())
continue;
- unsigned DstReg = MI->getOperand(0).getReg();
+ Register DstReg = MI->getOperand(0).getReg();
// Don't follow copies to physregs. These are usually setting up call
// arguments, and the argument registers are always call clobbered. We are
@@ -1162,7 +1162,7 @@
// Only virtual registers are rewritten.
if (Loc.isReg() && Loc.getReg() &&
Register::isVirtualRegister(Loc.getReg())) {
- unsigned VirtReg = Loc.getReg();
+ Register VirtReg = Loc.getReg();
if (VRM.isAssignedReg(VirtReg) &&
Register::isPhysicalRegister(VRM.getPhys(VirtReg))) {
// This can create a %noreg operand in rare cases when the sub-register
@@ -1258,7 +1258,7 @@
const TargetRegisterInfo &TRI) {
if (!LocMO.isReg())
return MBB->instr_end();
- unsigned Reg = LocMO.getReg();
+ Register Reg = LocMO.getReg();
// Find the next instruction in the MBB that define the register Reg.
while (I != MBB->end() && !I->isTerminator()) {
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index cc161e6..0781a0b 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -986,7 +986,7 @@
MO.setIsKill(false);
}
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (Register::isVirtualRegister(Reg)) {
@@ -1644,7 +1644,7 @@
unsigned Reg = LI.reg;
const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
for (unsigned I = 1; I < NumComp; ++I) {
- unsigned NewVReg = MRI->createVirtualRegister(RegClass);
+ Register NewVReg = MRI->createVirtualRegister(RegClass);
LiveInterval &NewLI = createEmptyInterval(NewVReg);
SplitLIs.push_back(&NewLI);
}
diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp
index 9836d3d..c2a1cc7 100644
--- a/llvm/lib/CodeGen/LivePhysRegs.cpp
+++ b/llvm/lib/CodeGen/LivePhysRegs.cpp
@@ -46,7 +46,7 @@
if (O->isReg()) {
if (!O->isDef() || O->isDebug())
continue;
- unsigned Reg = O->getReg();
+ Register Reg = O->getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
removeReg(Reg);
@@ -60,7 +60,7 @@
for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
if (!O->isReg() || !O->readsReg() || O->isDebug())
continue;
- unsigned Reg = O->getReg();
+ Register Reg = O->getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
addReg(Reg);
@@ -86,7 +86,7 @@
// Remove killed registers from the set.
for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
if (O->isReg() && !O->isDebug()) {
- unsigned Reg = O->getReg();
+ Register Reg = O->getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
if (O->isDef()) {
@@ -292,7 +292,7 @@
if (!MO->isReg() || !MO->isDef() || MO->isDebug())
continue;
- unsigned Reg = MO->getReg();
+ Register Reg = MO->getReg();
if (Reg == 0)
continue;
assert(Register::isPhysicalRegister(Reg));
@@ -309,7 +309,7 @@
if (!MO->isReg() || !MO->readsReg() || MO->isDebug())
continue;
- unsigned Reg = MO->getReg();
+ Register Reg = MO->getReg();
if (Reg == 0)
continue;
assert(Register::isPhysicalRegister(Reg));
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index d129129..d03e11f 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -32,7 +32,7 @@
LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg,
bool createSubRanges) {
- unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
+ Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
if (VRM)
VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
@@ -52,7 +52,7 @@
}
unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
- unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
+ Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
if (VRM) {
VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
}
@@ -308,7 +308,7 @@
MOE = MI->operands_end(); MOI != MOE; ++MOI) {
if (!MOI->isReg())
continue;
- unsigned Reg = MOI->getReg();
+ Register Reg = MOI->getReg();
if (!Register::isVirtualRegister(Reg)) {
// Check if MI reads any unreserved physregs.
if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
diff --git a/llvm/lib/CodeGen/LiveRangeShrink.cpp b/llvm/lib/CodeGen/LiveRangeShrink.cpp
index 08f82e0..cbf112e 100644
--- a/llvm/lib/CodeGen/LiveRangeShrink.cpp
+++ b/llvm/lib/CodeGen/LiveRangeShrink.cpp
@@ -172,7 +172,7 @@
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.isDead() || MO.isDebug())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// Do not move the instruction if it def/uses a physical register,
// unless it is a constant physical register or a noreg.
if (!Register::isVirtualRegister(Reg)) {
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index ce99e55..72c79e5 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -118,7 +118,7 @@
}
void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
- unsigned PhysReg = VRM->getPhys(VirtReg.reg);
+ Register PhysReg = VRM->getPhys(VirtReg.reg);
LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from "
<< printReg(PhysReg, TRI) << ':');
VRM->clearVirt(VirtReg.reg);
diff --git a/llvm/lib/CodeGen/LiveRegUnits.cpp b/llvm/lib/CodeGen/LiveRegUnits.cpp
index 0c1518b..97763de 100644
--- a/llvm/lib/CodeGen/LiveRegUnits.cpp
+++ b/llvm/lib/CodeGen/LiveRegUnits.cpp
@@ -47,7 +47,7 @@
if (O->isReg()) {
if (!O->isDef() || O->isDebug())
continue;
- unsigned Reg = O->getReg();
+ Register Reg = O->getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
removeReg(Reg);
@@ -59,7 +59,7 @@
for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
if (!O->isReg() || !O->readsReg() || O->isDebug())
continue;
- unsigned Reg = O->getReg();
+ Register Reg = O->getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
addReg(Reg);
@@ -70,7 +70,7 @@
// Add defs, uses and regmask clobbers to the set.
for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
if (O->isReg()) {
- unsigned Reg = O->getReg();
+ Register Reg = O->getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
if (!O->isDef() && !O->readsReg())
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 861f8ea..9557928 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -214,7 +214,7 @@
MachineOperand &MO = LastDef->getOperand(i);
if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
continue;
- unsigned DefReg = MO.getReg();
+ Register DefReg = MO.getReg();
if (TRI->isSubRegister(Reg, DefReg)) {
for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
SubRegs.isValid(); ++SubRegs)
@@ -519,7 +519,7 @@
}
if (!MO.isReg() || MO.getReg() == 0)
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (MO.isUse()) {
if (!(Register::isPhysicalRegister(MOReg) && MRI->isReserved(MOReg)))
MO.setIsKill(false);
@@ -690,7 +690,7 @@
MachineOperand &MO = MI.getOperand(i);
if (MO.isReg() && MO.isKill()) {
MO.setIsKill(false);
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isVirtualRegister(Reg)) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
diff --git a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
index 222432d..a9b4945 100644
--- a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
+++ b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
@@ -340,8 +340,8 @@
if (!MI->getOperand(1).isReg())
continue;
- const unsigned Dst = MI->getOperand(0).getReg();
- const unsigned Src = MI->getOperand(1).getReg();
+ const Register Dst = MI->getOperand(0).getReg();
+ const Register Src = MI->getOperand(1).getReg();
if (!Register::isVirtualRegister(Dst))
continue;
@@ -386,7 +386,7 @@
bool DoesMISideEffect = false;
if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
- const unsigned Dst = MI->getOperand(0).getReg();
+ const Register Dst = MI->getOperand(0).getReg();
DoesMISideEffect |= !Register::isVirtualRegister(Dst);
for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
@@ -754,7 +754,7 @@
for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
MachineInstr &MI = *MII++;
Changed = true;
- unsigned vRegToRename = MI.getOperand(0).getReg();
+ Register vRegToRename = MI.getOperand(0).getReg();
auto Rename = NVC.createVirtualRegister(vRegToRename);
std::vector<MachineOperand *> RenameMOs;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index de0e63a..f57a042 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -500,14 +500,14 @@
if (LiveIn)
for (;I != E && I->isCopy(); ++I)
if (I->getOperand(1).getReg() == PhysReg) {
- unsigned VirtReg = I->getOperand(0).getReg();
+ Register VirtReg = I->getOperand(0).getReg();
if (!MRI.constrainRegClass(VirtReg, RC))
llvm_unreachable("Incompatible live-in register class.");
return VirtReg;
}
// No luck, create a virtual register.
- unsigned VirtReg = MRI.createVirtualRegister(RC);
+ Register VirtReg = MRI.createVirtualRegister(RC);
BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
.addReg(PhysReg, RegState::Kill);
if (!LiveIn)
@@ -907,7 +907,7 @@
if (!OI->isReg() || OI->getReg() == 0 ||
!OI->isUse() || !OI->isKill() || OI->isUndef())
continue;
- unsigned Reg = OI->getReg();
+ Register Reg = OI->getReg();
if (Register::isPhysicalRegister(Reg) ||
LV->getVarInfo(Reg).removeKill(*MI)) {
KilledRegs.push_back(Reg);
@@ -928,7 +928,7 @@
if (!OI->isReg() || OI->getReg() == 0)
continue;
- unsigned Reg = OI->getReg();
+ Register Reg = OI->getReg();
if (!is_contained(UsedRegs, Reg))
UsedRegs.push_back(Reg);
}
@@ -1033,7 +1033,7 @@
for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
if (I->getOperand(ni+1).getMBB() == NMBB) {
MachineOperand &MO = I->getOperand(ni);
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
PHISrcRegs.insert(Reg);
if (MO.isUndef())
continue;
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 8f5778a..58d73f0 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -167,14 +167,14 @@
for (MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (!DefMI->isCopy())
continue;
- unsigned SrcReg = DefMI->getOperand(1).getReg();
+ Register SrcReg = DefMI->getOperand(1).getReg();
if (!Register::isVirtualRegister(SrcReg))
continue;
if (DefMI->getOperand(0).getSubReg())
@@ -280,7 +280,7 @@
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (Register::isVirtualRegister(Reg))
@@ -299,7 +299,7 @@
const MachineOperand &MO = MOP.value();
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (Register::isVirtualRegister(Reg))
@@ -376,7 +376,7 @@
return false;
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (Register::isVirtualRegister(MOReg))
continue;
if (PhysRefs.count(MOReg))
@@ -593,8 +593,8 @@
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned OldReg = MO.getReg();
- unsigned NewReg = CSMI->getOperand(i).getReg();
+ Register OldReg = MO.getReg();
+ Register NewReg = CSMI->getOperand(i).getReg();
// Go through implicit defs of CSMI and MI, if a def is not dead at MI,
// we should make sure it is not dead at CSMI.
@@ -822,8 +822,8 @@
assert(MI->getOperand(0).isDef() &&
"First operand of instr with one explicit def must be this def");
- unsigned VReg = MI->getOperand(0).getReg();
- unsigned NewReg = MRI->cloneVirtualRegister(VReg);
+ Register VReg = MI->getOperand(0).getReg();
+ Register NewReg = MRI->cloneVirtualRegister(VReg);
if (!isProfitableToCSE(NewReg, VReg, CMBB, MI))
continue;
MachineInstr &NewMI =
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index f3946b8..ebe76e3 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -119,8 +119,8 @@
void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) {
assert(MI->isCopy() && "Tracking non-copy?");
- unsigned Def = MI->getOperand(0).getReg();
- unsigned Src = MI->getOperand(1).getReg();
+ Register Def = MI->getOperand(0).getReg();
+ Register Src = MI->getOperand(1).getReg();
// Remember Def is defined by the copy.
for (MCRegUnitIterator RUI(Def, &TRI); RUI.isValid(); ++RUI)
@@ -163,8 +163,8 @@
// Check that the available copy isn't clobbered by any regmasks between
// itself and the destination.
- unsigned AvailSrc = AvailCopy->getOperand(1).getReg();
- unsigned AvailDef = AvailCopy->getOperand(0).getReg();
+ Register AvailSrc = AvailCopy->getOperand(1).getReg();
+ Register AvailDef = AvailCopy->getOperand(0).getReg();
for (const MachineInstr &MI :
make_range(AvailCopy->getIterator(), DestCopy.getIterator()))
for (const MachineOperand &MO : MI.operands())
@@ -262,8 +262,8 @@
/// isNopCopy("ecx = COPY eax", AH, CL) == false
static bool isNopCopy(const MachineInstr &PreviousCopy, unsigned Src,
unsigned Def, const TargetRegisterInfo *TRI) {
- unsigned PreviousSrc = PreviousCopy.getOperand(1).getReg();
- unsigned PreviousDef = PreviousCopy.getOperand(0).getReg();
+ Register PreviousSrc = PreviousCopy.getOperand(1).getReg();
+ Register PreviousDef = PreviousCopy.getOperand(0).getReg();
if (Src == PreviousSrc) {
assert(Def == PreviousDef);
return true;
@@ -300,7 +300,7 @@
// Copy was redundantly redefining either Src or Def. Remove earlier kill
// flags between Copy and PrevCopy because the value will be reused now.
assert(Copy.isCopy());
- unsigned CopyDef = Copy.getOperand(0).getReg();
+ Register CopyDef = Copy.getOperand(0).getReg();
assert(CopyDef == Src || CopyDef == Def);
for (MachineInstr &MI :
make_range(PrevCopy->getIterator(), Copy.getIterator()))
@@ -319,7 +319,7 @@
const MachineInstr &UseI,
unsigned UseIdx) {
- unsigned CopySrcReg = Copy.getOperand(1).getReg();
+ Register CopySrcReg = Copy.getOperand(1).getReg();
// If the new register meets the opcode register constraints, then allow
// forwarding.
@@ -410,9 +410,9 @@
if (!Copy)
continue;
- unsigned CopyDstReg = Copy->getOperand(0).getReg();
+ Register CopyDstReg = Copy->getOperand(0).getReg();
const MachineOperand &CopySrc = Copy->getOperand(1);
- unsigned CopySrcReg = CopySrc.getReg();
+ Register CopySrcReg = CopySrc.getReg();
// FIXME: Don't handle partial uses of wider COPYs yet.
if (MOUse.getReg() != CopyDstReg) {
@@ -468,8 +468,8 @@
// Analyze copies (which don't overlap themselves).
if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(),
MI->getOperand(1).getReg())) {
- unsigned Def = MI->getOperand(0).getReg();
- unsigned Src = MI->getOperand(1).getReg();
+ Register Def = MI->getOperand(0).getReg();
+ Register Src = MI->getOperand(1).getReg();
assert(!Register::isVirtualRegister(Def) &&
!Register::isVirtualRegister(Src) &&
@@ -504,7 +504,7 @@
for (const MachineOperand &MO : MI->implicit_operands()) {
if (!MO.isReg() || !MO.readsReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
ReadRegister(Reg, *MI, RegularUse);
@@ -527,7 +527,7 @@
for (const MachineOperand &MO : MI->implicit_operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
Tracker.clobberRegister(Reg, *TRI);
@@ -541,7 +541,7 @@
// Clobber any earlyclobber regs first.
for (const MachineOperand &MO : MI->operands())
if (MO.isReg() && MO.isEarlyClobber()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// If we have a tied earlyclobber, that means it is also read by this
// instruction, so we need to make sure we don't remove it as dead
// later.
@@ -560,7 +560,7 @@
RegMask = &MO;
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
@@ -583,7 +583,7 @@
MaybeDeadCopies.begin();
DI != MaybeDeadCopies.end();) {
MachineInstr *MaybeDead = *DI;
- unsigned Reg = MaybeDead->getOperand(0).getReg();
+ Register Reg = MaybeDead->getOperand(0).getReg();
assert(!MRI->isReserved(Reg));
if (!RegMask->clobbersPhysReg(Reg)) {
diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp
index 1bd7021..feb849c 100644
--- a/llvm/lib/CodeGen/MachineInstrBundle.cpp
+++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp
@@ -154,7 +154,7 @@
continue;
}
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
@@ -177,7 +177,7 @@
for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
MachineOperand &MO = *Defs[i];
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
@@ -329,7 +329,7 @@
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg || !Register::isPhysicalRegister(MOReg))
continue;
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index 3e80e8b..15c38da 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -424,7 +424,7 @@
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
assert(Register::isPhysicalRegister(Reg) &&
@@ -526,7 +526,7 @@
for (const MachineOperand &MO : TI->operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
@@ -554,7 +554,7 @@
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || MO.isDef() || !MO.getReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (PhysRegDefs.test(Reg) ||
PhysRegClobbers.test(Reg)) {
// If it's using a non-loop-invariant register, then it's obviously
@@ -852,7 +852,7 @@
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.isImplicit())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
@@ -922,7 +922,7 @@
// Check that all register operands are caller-preserved physical registers.
for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// If operand is a virtual register, check if it comes from a copy of a
// physical register.
if (Register::isVirtualRegister(Reg))
@@ -955,14 +955,14 @@
const MachineFunction *MF = MI.getMF();
// Check that we are copying a constant physical register.
- unsigned CopySrcReg = MI.getOperand(1).getReg();
+ Register CopySrcReg = MI.getOperand(1).getReg();
if (Register::isVirtualRegister(CopySrcReg))
return false;
if (!TRI->isCallerPreservedPhysReg(CopySrcReg, *MF))
return false;
- unsigned CopyDstReg = MI.getOperand(0).getReg();
+ Register CopyDstReg = MI.getOperand(0).getReg();
// Check if any of the uses of the copy are invariant stores.
assert(Register::isVirtualRegister(CopyDstReg) &&
"copy dst is not a virtual reg");
@@ -1010,7 +1010,7 @@
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
// Don't hoist an instruction that uses or defines a physical register.
@@ -1061,7 +1061,7 @@
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
@@ -1104,7 +1104,7 @@
const MachineOperand &MO = UseMI.getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (MOReg != Reg)
continue;
@@ -1132,7 +1132,7 @@
if (!DefMO.isReg() || !DefMO.isDef())
continue;
--NumDefs;
- unsigned Reg = DefMO.getReg();
+ Register Reg = DefMO.getReg();
if (Register::isPhysicalRegister(Reg))
continue;
@@ -1225,7 +1225,7 @@
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || MO.isImplicit())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) {
@@ -1304,7 +1304,7 @@
MachineFunction &MF = *MI->getMF();
const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
// Ok, we're unfolding. Create a temporary register and do the unfold.
- unsigned Reg = MRI->createVirtualRegister(RC);
+ Register Reg = MRI->createVirtualRegister(RC);
SmallVector<MachineInstr *, 2> NewMIs;
bool Success = TII->unfoldMemoryOperand(MF, *MI, Reg,
@@ -1390,8 +1390,8 @@
SmallVector<const TargetRegisterClass*, 2> OrigRCs;
for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
unsigned Idx = Defs[i];
- unsigned Reg = MI->getOperand(Idx).getReg();
- unsigned DupReg = Dup->getOperand(Idx).getReg();
+ Register Reg = MI->getOperand(Idx).getReg();
+ Register DupReg = Dup->getOperand(Idx).getReg();
OrigRCs.push_back(MRI->getRegClass(DupReg));
if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
@@ -1403,8 +1403,8 @@
}
for (unsigned Idx : Defs) {
- unsigned Reg = MI->getOperand(Idx).getReg();
- unsigned DupReg = Dup->getOperand(Idx).getReg();
+ Register Reg = MI->getOperand(Idx).getReg();
+ Register DupReg = Dup->getOperand(Idx).getReg();
MRI->replaceRegWith(Reg, DupReg);
MRI->clearKillFlags(DupReg);
}
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 43081cc..c7e804f 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -750,7 +750,7 @@
printTargetFlags(OS, *this);
switch (getType()) {
case MachineOperand::MO_Register: {
- unsigned Reg = getReg();
+ Register Reg = getReg();
if (isImplicit())
OS << (isDef() ? "implicit-def " : "implicit ");
else if (PrintDef && isDef())
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index ca7d694..584b2a1 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -349,7 +349,7 @@
// If the operand uses a subregister, replace it with a new register
// without subregisters, and generate a copy to the new register.
- unsigned NewReg = MRI.createVirtualRegister(RC);
+ Register NewReg = MRI.createVirtualRegister(RC);
MachineBasicBlock &PredB = *PI.getOperand(i+1).getMBB();
MachineBasicBlock::iterator At = PredB.getFirstTerminator();
const DebugLoc &DL = PredB.findDebugLoc(At);
@@ -730,7 +730,7 @@
MOI != MOE; ++MOI) {
if (!MOI->isReg())
continue;
- unsigned Reg = MOI->getReg();
+ Register Reg = MOI->getReg();
if (MOI->isDef()) {
// If the register is used by a Phi, then create an anti dependence.
for (MachineRegisterInfo::use_instr_iterator
@@ -809,7 +809,7 @@
continue;
// Get the MI and SUnit for the instruction that defines the original base.
- unsigned OrigBase = I.getInstr()->getOperand(BasePos).getReg();
+ Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();
MachineInstr *DefMI = MRI.getUniqueVRegDef(OrigBase);
if (!DefMI)
continue;
@@ -1514,7 +1514,7 @@
continue;
for (const MachineOperand &MO : MI->operands())
if (MO.isReg() && MO.isUse()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isVirtualRegister(Reg))
Uses.insert(Reg);
else if (MRI.isAllocatable(Reg))
@@ -1525,7 +1525,7 @@
for (SUnit *SU : NS)
for (const MachineOperand &MO : SU->getInstr()->operands())
if (MO.isReg() && MO.isDef() && !MO.isDead()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isVirtualRegister(Reg)) {
if (!Uses.count(Reg))
LiveOutRegs.push_back(RegisterMaskPair(Reg,
@@ -2311,7 +2311,7 @@
for (MachineBasicBlock::iterator BBI = BB->instr_begin(),
BBE = BB->getFirstNonPHI();
BBI != BBE; ++BBI) {
- unsigned Def = BBI->getOperand(0).getReg();
+ Register Def = BBI->getOperand(0).getReg();
unsigned InitVal = 0;
unsigned LoopVal = 0;
@@ -2558,7 +2558,7 @@
int StageScheduled = Schedule.stageScheduled(getSUnit(&*BBI));
assert(StageScheduled != -1 && "Expecting scheduled instruction.");
- unsigned Def = MO.getReg();
+ Register Def = MO.getReg();
unsigned NumPhis = Schedule.getStagesForReg(Def, CurStageNum);
// An instruction scheduled in stage 0 and is used after the loop
// requires a phi in the epilog for the last definition from either
@@ -2591,7 +2591,7 @@
PhiOp2 = VRMap[PrevStage - np][Def];
const TargetRegisterClass *RC = MRI.getRegClass(Def);
- unsigned NewReg = MRI.createVirtualRegister(RC);
+ Register NewReg = MRI.createVirtualRegister(RC);
MachineInstrBuilder NewPhi =
BuildMI(*NewBB, NewBB->getFirstNonPHI(), DebugLoc(),
@@ -2656,7 +2656,7 @@
MOI != MOE; ++MOI) {
if (!MOI->isReg() || !MOI->isDef())
continue;
- unsigned reg = MOI->getReg();
+ Register reg = MOI->getReg();
// Assume physical registers are used, unless they are marked dead.
if (Register::isPhysicalRegister(reg)) {
used = !MOI->isDead();
@@ -2694,7 +2694,7 @@
BBI != BBE;) {
MachineInstr *MI = &*BBI;
++BBI;
- unsigned reg = MI->getOperand(0).getReg();
+ Register reg = MI->getOperand(0).getReg();
if (MRI.use_begin(reg) == MRI.use_end()) {
LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
@@ -2717,7 +2717,7 @@
SMSchedule &Schedule) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
for (auto &PHI : KernelBB->phis()) {
- unsigned Def = PHI.getOperand(0).getReg();
+ Register Def = PHI.getOperand(0).getReg();
// Check for any Phi definition that used as an operand of another Phi
// in the same block.
for (MachineRegisterInfo::use_instr_iterator I = MRI.use_instr_begin(Def),
@@ -2854,7 +2854,7 @@
if (!BaseOp->isReg())
return false;
- unsigned BaseReg = BaseOp->getReg();
+ Register BaseReg = BaseOp->getReg();
MachineRegisterInfo &MRI = MF.getRegInfo();
// Check if there is a Phi. If so, get the definition in the loop.
@@ -2964,11 +2964,11 @@
MachineOperand &MO = NewMI->getOperand(i);
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
continue;
- unsigned reg = MO.getReg();
+ Register reg = MO.getReg();
if (MO.isDef()) {
// Create a new virtual register for the definition.
const TargetRegisterClass *RC = MRI.getRegClass(reg);
- unsigned NewReg = MRI.createVirtualRegister(RC);
+ Register NewReg = MRI.createVirtualRegister(RC);
MO.setReg(NewReg);
VRMap[CurStageNum][reg] = NewReg;
if (LastDef)
@@ -3051,7 +3051,7 @@
unsigned InitVal = 0;
unsigned LoopVal = 0;
getPhiRegs(PHI, BB, InitVal, LoopVal);
- unsigned PhiDef = PHI.getOperand(0).getReg();
+ Register PhiDef = PHI.getOperand(0).getReg();
unsigned PhiStage =
(unsigned)Schedule.stageScheduled(getSUnit(MRI.getVRegDef(PhiDef)));
@@ -3147,7 +3147,7 @@
unsigned BasePosLd, OffsetPosLd;
if (!TII->getBaseAndOffsetPosition(*MI, BasePosLd, OffsetPosLd))
return false;
- unsigned BaseReg = MI->getOperand(BasePosLd).getReg();
+ Register BaseReg = MI->getOperand(BasePosLd).getReg();
// Look for the Phi instruction.
MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
@@ -3202,7 +3202,7 @@
unsigned BasePos, OffsetPos;
if (!TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
return;
- unsigned BaseReg = MI->getOperand(BasePos).getReg();
+ Register BaseReg = MI->getOperand(BasePos).getReg();
MachineInstr *LoopDef = findDefInLoop(BaseReg);
int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef));
int DefCycleNum = Schedule.cycleScheduled(getSUnit(LoopDef));
@@ -3502,7 +3502,7 @@
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
unsigned BasePos, OffsetPos;
if (ST.getInstrInfo()->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
if (MI->getOperand(BasePos).getReg() == Reg)
@@ -3857,7 +3857,7 @@
if (!Op.isReg() || !Op.isDef())
continue;
- unsigned Reg = Op.getReg();
+ Register Reg = Op.getReg();
unsigned MaxDiff = 0;
bool PhiIsSwapped = false;
for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(Reg),
diff --git a/llvm/lib/CodeGen/MachineSSAUpdater.cpp b/llvm/lib/CodeGen/MachineSSAUpdater.cpp
index e8b4204..3370b52 100644
--- a/llvm/lib/CodeGen/MachineSSAUpdater.cpp
+++ b/llvm/lib/CodeGen/MachineSSAUpdater.cpp
@@ -95,7 +95,7 @@
while (I != BB->end() && I->isPHI()) {
bool Same = true;
for (unsigned i = 1, e = I->getNumOperands(); i != e; i += 2) {
- unsigned SrcReg = I->getOperand(i).getReg();
+ Register SrcReg = I->getOperand(i).getReg();
MachineBasicBlock *SrcBB = I->getOperand(i+1).getMBB();
if (AVals[SrcBB] != SrcReg) {
Same = false;
@@ -118,7 +118,7 @@
const TargetRegisterClass *RC,
MachineRegisterInfo *MRI,
const TargetInstrInfo *TII) {
- unsigned NewVR = MRI->createVirtualRegister(RC);
+ Register NewVR = MRI->createVirtualRegister(RC);
return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index ea322bf..a46ded9 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -933,7 +933,7 @@
if (TrackLaneMasks && !MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
@@ -1687,12 +1687,12 @@
// Check for pure vreg copies.
const MachineOperand &SrcOp = Copy->getOperand(1);
- unsigned SrcReg = SrcOp.getReg();
+ Register SrcReg = SrcOp.getReg();
if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
return;
const MachineOperand &DstOp = Copy->getOperand(0);
- unsigned DstReg = DstOp.getReg();
+ Register DstReg = DstOp.getReg();
if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
return;
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 3ebb76d..3d5530d 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -195,8 +195,8 @@
if (!MI.isCopy())
return false;
- unsigned SrcReg = MI.getOperand(1).getReg();
- unsigned DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
if (!Register::isVirtualRegister(SrcReg) ||
!Register::isVirtualRegister(DstReg) || !MRI->hasOneNonDBGUse(SrcReg))
return false;
@@ -414,7 +414,7 @@
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0)
continue;
@@ -613,7 +613,7 @@
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue; // Ignore non-register operands.
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0) continue;
if (Register::isPhysicalRegister(Reg)) {
@@ -815,7 +815,7 @@
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0 || !Register::isPhysicalRegister(Reg))
continue;
if (SuccToSinkTo->isLiveIn(Reg))
@@ -1029,7 +1029,7 @@
const TargetRegisterInfo *TRI) {
for (auto U : UsedOpsInCopy) {
MachineOperand &MO = MI->getOperand(U);
- unsigned SrcReg = MO.getReg();
+ Register SrcReg = MO.getReg();
if (!UsedRegUnits.available(SrcReg)) {
MachineBasicBlock::iterator NI = std::next(MI->getIterator());
for (MachineInstr &UI : make_range(NI, CurBB.end())) {
@@ -1052,7 +1052,7 @@
for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S)
SuccBB->removeLiveIn(*S);
for (auto U : UsedOpsInCopy) {
- unsigned Reg = MI->getOperand(U).getReg();
+ Register Reg = MI->getOperand(U).getReg();
if (!SuccBB->isLiveIn(Reg))
SuccBB->addLiveIn(Reg);
}
@@ -1068,7 +1068,7 @@
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (MO.isDef()) {
@@ -1181,7 +1181,7 @@
for (auto &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned reg = MO.getReg();
+ Register reg = MO.getReg();
for (auto *MI : SeenDbgInstrs.lookup(reg))
DbgValsToSink.push_back(MI);
}
diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
index 8f382fd..66a3bc2 100644
--- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
@@ -660,7 +660,7 @@
const MachineOperand &MO = *I;
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
if (Register::isPhysicalRegister(Reg)) {
@@ -687,7 +687,7 @@
assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI");
for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) {
if (UseMI.getOperand(i + 1).getMBB() == Pred) {
- unsigned Reg = UseMI.getOperand(i).getReg();
+ Register Reg = UseMI.getOperand(i).getReg();
Deps.push_back(DataDep(MRI, Reg, i));
return;
}
@@ -708,7 +708,7 @@
const MachineOperand &MO = *MI;
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
// Track live defs and kills for updating RegUnits.
@@ -902,7 +902,7 @@
const MachineOperand &MO = *MOI;
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isPhysicalRegister(Reg))
continue;
if (MO.readsReg())
@@ -930,7 +930,7 @@
// Now we know the height of MI. Update any regunits read.
for (unsigned i = 0, e = ReadOps.size(); i != e; ++i) {
- unsigned Reg = MI.getOperand(ReadOps[i]).getReg();
+ Register Reg = MI.getOperand(ReadOps[i]).getReg();
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
LiveRegUnit &LRU = RegUnits[*Units];
// Set the height to the highest reader of the unit.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 33d2246..c0c5a70 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1609,7 +1609,7 @@
switch (MO->getType()) {
case MachineOperand::MO_Register: {
- const unsigned Reg = MO->getReg();
+ const Register Reg = MO->getReg();
if (!Reg)
return;
if (MRI->tracksLiveness() && !MI->isDebugValue())
@@ -2184,7 +2184,7 @@
if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
MODef.isEarlyClobber() || MODef.isDebug())
report("Unexpected flag on PHI operand", &MODef, 0);
- unsigned DefReg = MODef.getReg();
+ Register DefReg = MODef.getReg();
if (!Register::isVirtualRegister(DefReg))
report("Expected first PHI operand to be a virtual register", &MODef, 0);
diff --git a/llvm/lib/CodeGen/OptimizePHIs.cpp b/llvm/lib/CodeGen/OptimizePHIs.cpp
index 3a8c711..1a49396 100644
--- a/llvm/lib/CodeGen/OptimizePHIs.cpp
+++ b/llvm/lib/CodeGen/OptimizePHIs.cpp
@@ -97,7 +97,7 @@
unsigned &SingleValReg,
InstrSet &PHIsInCycle) {
assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
- unsigned DstReg = MI->getOperand(0).getReg();
+ Register DstReg = MI->getOperand(0).getReg();
// See if we already saw this register.
if (!PHIsInCycle.insert(MI).second)
@@ -109,7 +109,7 @@
// Scan the PHI operands.
for (unsigned i = 1; i != MI->getNumOperands(); i += 2) {
- unsigned SrcReg = MI->getOperand(i).getReg();
+ Register SrcReg = MI->getOperand(i).getReg();
if (SrcReg == DstReg)
continue;
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
@@ -141,7 +141,7 @@
/// other PHIs in a cycle.
bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) {
assert(MI->isPHI() && "IsDeadPHICycle expects a PHI instruction");
- unsigned DstReg = MI->getOperand(0).getReg();
+ Register DstReg = MI->getOperand(0).getReg();
assert(Register::isVirtualRegister(DstReg) &&
"PHI destination is not a virtual register");
@@ -176,7 +176,7 @@
InstrSet PHIsInCycle;
if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) &&
SingleValReg != 0) {
- unsigned OldReg = MI->getOperand(0).getReg();
+ Register OldReg = MI->getOperand(0).getReg();
if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
continue;
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index eea32bd..2b3ce89 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -168,7 +168,7 @@
// Remove dead IMPLICIT_DEF instructions.
for (MachineInstr *DefMI : ImpDefs) {
- unsigned DefReg = DefMI->getOperand(0).getReg();
+ Register DefReg = DefMI->getOperand(0).getReg();
if (MRI->use_nodbg_empty(DefReg)) {
if (LIS)
LIS->RemoveMachineInstrFromMaps(*DefMI);
@@ -240,7 +240,7 @@
MachineInstr *MPhi = MBB.remove(&*MBB.begin());
unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
- unsigned DestReg = MPhi->getOperand(0).getReg();
+ Register DestReg = MPhi->getOperand(0).getReg();
assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
bool isDead = MPhi->getOperand(0).isDead();
@@ -368,7 +368,7 @@
// IncomingReg register in the corresponding predecessor basic block.
SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
for (int i = NumSrcs - 1; i >= 0; --i) {
- unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
+ Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
isImplicitlyDefined(SrcReg, *MRI);
@@ -567,7 +567,7 @@
for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
BBI != BBE && BBI->isPHI(); ++BBI) {
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
- unsigned Reg = BBI->getOperand(i).getReg();
+ Register Reg = BBI->getOperand(i).getReg();
MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
// Is there a critical edge from PreMBB to MBB?
if (PreMBB->succ_size() == 1)
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index a41ac73..e613d07 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -581,7 +581,7 @@
MRI->constrainRegClass(DstReg, DstRC);
}
- unsigned NewVR = MRI->createVirtualRegister(RC);
+ Register NewVR = MRI->createVirtualRegister(RC);
MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVR)
.addReg(DstReg, 0, SubIdx);
@@ -761,7 +761,7 @@
// NewRC is only correct if no subregisters are involved. findNextSource()
// should have rejected those cases already.
assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand");
- unsigned NewVR = MRI.createVirtualRegister(NewRC);
+ Register NewVR = MRI.createVirtualRegister(NewRC);
MachineBasicBlock *MBB = OrigPHI.getParent();
MachineInstrBuilder MIB = BuildMI(*MBB, &OrigPHI, OrigPHI.getDebugLoc(),
TII.get(TargetOpcode::PHI), NewVR);
@@ -1229,7 +1229,7 @@
// Insert the COPY.
const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
- unsigned NewVReg = MRI->createVirtualRegister(DefRC);
+ Register NewVReg = MRI->createVirtualRegister(DefRC);
MachineInstr *NewCopy =
BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
@@ -1315,7 +1315,7 @@
if (MCID.getNumDefs() != 1)
return false;
- unsigned Reg = MI.getOperand(0).getReg();
+ Register Reg = MI.getOperand(0).getReg();
// To reduce compilation time, we check MRI->hasOneNonDBGUser when inserting
// loads. It should be checked when processing uses of the load, since
// uses can be removed during peephole.
@@ -1335,7 +1335,7 @@
return false;
if (MCID.getNumDefs() != 1)
return false;
- unsigned Reg = MI.getOperand(0).getReg();
+ Register Reg = MI.getOperand(0).getReg();
if (Register::isVirtualRegister(Reg)) {
ImmDefMIs.insert(std::make_pair(Reg, &MI));
ImmDefRegs.insert(Reg);
@@ -1358,7 +1358,7 @@
// Ignore dead implicit defs.
if (MO.isImplicit() && MO.isDead())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (ImmDefRegs.count(Reg) == 0)
@@ -1392,11 +1392,11 @@
DenseMap<unsigned, MachineInstr *> &CopyMIs) {
assert(MI.isCopy() && "expected a COPY machine instruction");
- unsigned SrcReg = MI.getOperand(1).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
if (!Register::isVirtualRegister(SrcReg))
return false;
- unsigned DstReg = MI.getOperand(0).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
if (!Register::isVirtualRegister(DstReg))
return false;
@@ -1415,7 +1415,7 @@
if (SrcSubReg != PrevSrcSubReg)
return false;
- unsigned PrevDstReg = PrevCopy->getOperand(0).getReg();
+ Register PrevDstReg = PrevCopy->getOperand(0).getReg();
// Only replace if the copy register class is the same.
//
@@ -1442,8 +1442,8 @@
if (DisableNAPhysCopyOpt)
return false;
- unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
if (isNAPhysCopy(SrcReg) && Register::isVirtualRegister(DstReg)) {
// %vreg = COPY %physreg
// Avoid using a datastructure which can track multiple live non-allocatable
@@ -1465,7 +1465,7 @@
return false;
}
- unsigned PrevDstReg = PrevCopy->second->getOperand(0).getReg();
+ Register PrevDstReg = PrevCopy->second->getOperand(0).getReg();
if (PrevDstReg == SrcReg) {
// Remove the virt->phys copy: we saw the virtual register definition, and
// the non-allocatable physical register's state hasn't changed since then.
@@ -1660,7 +1660,7 @@
for (const MachineOperand &MO : MI->operands()) {
// Visit all operands: definitions can be implicit or explicit.
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (MO.isDef() && isNAPhysCopy(Reg)) {
const auto &Def = NAPhysToVirtMIs.find(Reg);
if (Def != NAPhysToVirtMIs.end()) {
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index 1fd055c..11bff45 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -73,7 +73,7 @@
void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
LLVM_DEBUG(dbgs() << "Processing " << *MI);
- unsigned Reg = MI->getOperand(0).getReg();
+ Register Reg = MI->getOperand(0).getReg();
if (Register::isVirtualRegister(Reg)) {
// For virtual registers, mark all uses as <undef>, and convert users to
@@ -100,7 +100,7 @@
for (MachineOperand &MO : UserMI->operands()) {
if (!MO.isReg())
continue;
- unsigned UserReg = MO.getReg();
+ Register UserReg = MO.getReg();
if (!Register::isPhysicalRegister(UserReg) ||
!TRI->regsOverlap(Reg, UserReg))
continue;
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index fbf81c2..44d0233 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -455,7 +455,7 @@
if (MO.isUndef())
return;
- unsigned PhysReg = MO.getReg();
+ Register PhysReg = MO.getReg();
assert(Register::isPhysicalRegister(PhysReg) && "Bad usePhysReg operand");
markRegUsedInInstr(PhysReg);
@@ -645,7 +645,7 @@
unsigned C = 0;
for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
if (isCoalescable(MI)) {
- unsigned Reg = MI.getOperand(1).getReg();
+ Register Reg = MI.getOperand(1).getReg();
Reg = traceCopyChain(Reg);
if (Reg != 0)
return Reg;
@@ -750,7 +750,7 @@
void RegAllocFast::allocVirtRegUndef(MachineOperand &MO) {
assert(MO.isUndef() && "expected undef use");
- unsigned VirtReg = MO.getReg();
+ Register VirtReg = MO.getReg();
assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg");
LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
@@ -889,7 +889,7 @@
SmallSet<unsigned, 8> ThroughRegs;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) ||
@@ -904,7 +904,7 @@
LLVM_DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg))
continue;
markRegUsedInInstr(Reg);
@@ -919,7 +919,7 @@
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isUse()) {
@@ -945,7 +945,7 @@
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (!MO.isEarlyClobber())
@@ -960,7 +960,7 @@
UsedInInstr.clear();
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg))
continue;
LLVM_DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI)
@@ -1043,7 +1043,7 @@
continue;
}
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg) continue;
if (Register::isVirtualRegister(Reg)) {
VirtOpEnd = i+1;
@@ -1094,7 +1094,7 @@
for (unsigned I = 0; I != VirtOpEnd; ++I) {
MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isUse()) {
@@ -1123,7 +1123,7 @@
for (MachineOperand &MO : MI.uses()) {
if (!MO.isReg() || !MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
@@ -1138,7 +1138,7 @@
if (hasEarlyClobbers) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg))
continue;
// Look for physreg defs and tied uses.
@@ -1166,7 +1166,7 @@
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg) || !MRI->isAllocatable(Reg))
continue;
@@ -1179,7 +1179,7 @@
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// We have already dealt with phys regs in the previous scan.
if (Register::isPhysicalRegister(Reg))
@@ -1214,7 +1214,7 @@
// mostly constants and frame indices.
if (!MO.isReg())
return;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
return;
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 10289ef..d27db67 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2919,7 +2919,7 @@
SmallVector<unsigned, 2> RecoloringCandidates;
HintsInfo Info;
unsigned Reg = VirtReg.reg;
- unsigned PhysReg = VRM->getPhys(Reg);
+ Register PhysReg = VRM->getPhys(Reg);
// Start the recoloring algorithm from the input live-interval, then
// it will propagate to the ones that are copy-related with it.
Visited.insert(Reg);
@@ -2940,7 +2940,7 @@
// Get the live interval mapped with this virtual register to be able
// to check for the interference with the new color.
LiveInterval &LI = LIS->getInterval(Reg);
- unsigned CurrPhys = VRM->getPhys(Reg);
+ Register CurrPhys = VRM->getPhys(Reg);
// Check that the new color matches the register class constraints and
// that it is free for this live range.
if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index b91b495..6ff5ddb 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -802,7 +802,7 @@
return { false, false };
MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
- unsigned NewReg = NewDstMO.getReg();
+ Register NewReg = NewDstMO.getReg();
if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
return { false, false };
@@ -1240,7 +1240,7 @@
return false;
// Only support subregister destinations when the def is read-undef.
MachineOperand &DstOperand = CopyMI->getOperand(0);
- unsigned CopyDstReg = DstOperand.getReg();
+ Register CopyDstReg = DstOperand.getReg();
if (DstOperand.getSubReg() && !DstOperand.isUndef())
return false;
@@ -2411,7 +2411,7 @@
assert(MI && "No defining instruction");
if (!MI->isFullCopy())
return std::make_pair(VNI, TrackReg);
- unsigned SrcReg = MI->getOperand(1).getReg();
+ Register SrcReg = MI->getOperand(1).getReg();
if (!Register::isVirtualRegister(SrcReg))
return std::make_pair(VNI, TrackReg);
@@ -3189,7 +3189,7 @@
MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
assert(MI && "No instruction to erase");
if (MI->isCopy()) {
- unsigned Reg = MI->getOperand(1).getReg();
+ Register Reg = MI->getOperand(1).getReg();
if (Register::isVirtualRegister(Reg) && Reg != CP.getSrcReg() &&
Reg != CP.getDstReg())
ShrinkRegs.push_back(Reg);
@@ -3463,8 +3463,8 @@
if (Copy->getOperand(1).isUndef())
return false;
- unsigned SrcReg = Copy->getOperand(1).getReg();
- unsigned DstReg = Copy->getOperand(0).getReg();
+ Register SrcReg = Copy->getOperand(1).getReg();
+ Register DstReg = Copy->getOperand(0).getReg();
if (Register::isPhysicalRegister(SrcReg) ||
Register::isPhysicalRegister(DstReg))
return false;
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 8a28763..bf192d1 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -499,7 +499,7 @@
void collectOperand(const MachineOperand &MO) const {
if (!MO.isReg() || !MO.getReg())
return;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (MO.isUse()) {
if (!MO.isUndef() && !MO.isInternalRead())
pushReg(Reg, RegOpers.Uses);
@@ -530,7 +530,7 @@
void collectOperandLanes(const MachineOperand &MO) const {
if (!MO.isReg() || !MO.getReg())
return;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
unsigned SubRegIdx = MO.getSubReg();
if (MO.isUse()) {
if (!MO.isUndef() && !MO.isInternalRead())
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 8ddd511..3f48b1d 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -133,7 +133,7 @@
}
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
continue;
@@ -204,7 +204,7 @@
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
continue;
if (MO.isUse()) {
@@ -694,7 +694,7 @@
for (const MachineOperand &MO : NMI.operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// We only care about virtual registers and ignore virtual registers
// created by the target callbacks in the process (those will be handled
// in a scavenging round).
@@ -716,7 +716,7 @@
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// Only vregs, no newly created vregs (see above).
if (!Register::isVirtualRegister(Reg) ||
Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 35635ad..e3f5abb 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -138,7 +138,7 @@
LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
++I) {
- unsigned NewVReg = MRI->createVirtualRegister(RegClass);
+ Register NewVReg = MRI->createVirtualRegister(RegClass);
LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
Intervals.push_back(&NewLI);
LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg));
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 9d4e00d..af07f8f 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -205,7 +205,7 @@
if (ExitMI) {
for (const MachineOperand &MO : ExitMI->operands()) {
if (!MO.isReg() || MO.isDef()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg)) {
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
} else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
@@ -285,7 +285,7 @@
void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
MachineInstr *MI = SU->getInstr();
MachineOperand &MO = MI->getOperand(OperIdx);
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// We do not need to track any dependencies for constant registers.
if (MRI.isConstantPhysReg(Reg))
return;
@@ -361,7 +361,7 @@
LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
{
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// No point in tracking lanemasks if we don't have interesting subregisters.
const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
if (!RC.HasDisjunctSubRegs)
@@ -382,7 +382,7 @@
void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
MachineInstr *MI = SU->getInstr();
MachineOperand &MO = MI->getOperand(OperIdx);
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
LaneBitmask DefLaneMask;
LaneBitmask KillLaneMask;
@@ -491,7 +491,7 @@
void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
const MachineInstr *MI = SU->getInstr();
const MachineOperand &MO = MI->getOperand(OperIdx);
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// Remember the use. Data dependencies will be added when we find the def.
LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
@@ -821,7 +821,7 @@
const MachineOperand &MO = MI.getOperand(j);
if (!MO.isReg() || !MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg)) {
addPhysRegDeps(SU, j);
} else if (Register::isVirtualRegister(Reg)) {
@@ -838,7 +838,7 @@
// additional use dependencies.
if (!MO.isReg() || !MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isPhysicalRegister(Reg)) {
addPhysRegDeps(SU, j);
} else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
@@ -1071,7 +1071,7 @@
for (MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.readsReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
@@ -1102,7 +1102,7 @@
if (MO.isReg()) {
if (!MO.isDef())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg)
continue;
LiveRegs.removeReg(Reg);
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index d42ce27..3ad9c41 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -272,7 +272,7 @@
// does not include operand register class info.
const TargetRegisterClass *RC = TLI->getRegClassFor(
Op.getSimpleValueType(), Op.getNode()->isDivergent());
- unsigned VReg = MRI->createVirtualRegister(RC);
+ Register VReg = MRI->createVirtualRegister(RC);
BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
return VReg;
@@ -319,7 +319,7 @@
if (!ConstrainedRC) {
OpRC = TRI->getAllocatableClass(OpRC);
assert(OpRC && "Constraints cannot be fulfilled for allocation");
- unsigned NewVReg = MRI->createVirtualRegister(OpRC);
+ Register NewVReg = MRI->createVirtualRegister(OpRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
@@ -386,7 +386,7 @@
: nullptr;
if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
- unsigned NewVReg = MRI->createVirtualRegister(IIRC);
+ Register NewVReg = MRI->createVirtualRegister(IIRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
@@ -464,7 +464,7 @@
// register instead.
RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
assert(RC && "No legal register class for VT supports that SubIdx");
- unsigned NewReg = MRI->createVirtualRegister(RC);
+ Register NewReg = MRI->createVirtualRegister(RC);
BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
.addReg(VReg);
return NewReg;
@@ -613,7 +613,7 @@
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
const TargetRegisterClass *DstRC =
TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
- unsigned NewVReg = MRI->createVirtualRegister(DstRC);
+ Register NewVReg = MRI->createVirtualRegister(DstRC);
BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
NewVReg).addReg(VReg);
@@ -630,7 +630,7 @@
bool IsClone, bool IsCloned) {
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
- unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
+ Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
unsigned NumOps = Node->getNumOperands();
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 9718a13..7468ba5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -808,7 +808,7 @@
} else {
// Copy from physical register.
assert(I->getReg() && "Unknown physical register!");
- unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
+ Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
(void)isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 71d0022..df553cc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4117,7 +4117,7 @@
SDValue Src = getValue(SrcV);
// Create a virtual register, then update the virtual register.
- unsigned VReg =
+ Register VReg =
SwiftError.getOrCreateVRegDefAt(&I, FuncInfo.MBB, I.getPointerOperand());
// Chain, DL, Reg, N or Chain, DL, Reg, N, Glue
// Chain can be getRoot or getControlRoot.
@@ -7154,7 +7154,7 @@
if (SwiftErrorVal && TLI.supportSwiftError()) {
// Get the last element of InVals.
SDValue Src = CLI.InVals.back();
- unsigned VReg = SwiftError.getOrCreateVRegDefAt(
+ Register VReg = SwiftError.getOrCreateVRegDefAt(
CS.getInstruction(), FuncInfo.MBB, SwiftErrorVal);
SDValue CopyNode = CLI.DAG.getCopyToReg(Result.second, CLI.DL, VReg, Src);
DAG.setRoot(CopyNode);
@@ -9725,7 +9725,8 @@
MachineFunction& MF = SDB->DAG.getMachineFunction();
MachineRegisterInfo& RegInfo = MF.getRegInfo();
- unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
+ Register SRetReg =
+ RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
FuncInfo->DemoteRegister = SRetReg;
NewRoot =
SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b03c388..b1d6b69 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -79,7 +79,7 @@
const CCValAssign &ArgLoc = ArgLocs[I];
if (!ArgLoc.isRegLoc())
continue;
- unsigned Reg = ArgLoc.getLocReg();
+ Register Reg = ArgLoc.getLocReg();
// Only look at callee saved registers.
if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
continue;
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 36f2da2..412a000 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -278,7 +278,7 @@
// Ignore instructions like DBG_VALUE which don't read/def the register.
if (!MO.isDef() && !MO.readsReg())
continue;
- unsigned PhysReg = MO.getReg();
+ Register PhysReg = MO.getReg();
if (!PhysReg)
continue;
assert(Register::isPhysicalRegister(PhysReg) && "Unallocated register?!");
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index 5c944fe..4e4971d 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -437,7 +437,7 @@
assert(DefMI != nullptr);
LaneBitmask LM;
for (const MachineOperand &DefOp : DefMI->defs()) {
- unsigned R = DefOp.getReg();
+ Register R = DefOp.getReg();
if (R != LI.reg)
continue;
if (unsigned SR = DefOp.getSubReg())
@@ -1373,7 +1373,7 @@
assert(LI.hasSubRanges());
LiveRangeCalc SubLRC;
- unsigned Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
+ Register Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
: MRI.getMaxLaneMaskForVReg(Reg);
for (LiveInterval::SubRange &S : LI.subranges()) {
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 6e1b86f..f4e6aa2 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -113,7 +113,7 @@
unsigned Size = DL.getPointerSizeInBits();
assert((Size % 8) == 0 && "Need pointer size in bytes.");
Size /= 8;
- unsigned Reg = (++MOI)->getReg();
+ Register Reg = (++MOI)->getReg();
int64_t Imm = (++MOI)->getImm();
Locs.emplace_back(StackMaps::Location::Direct, Size,
getDwarfRegNum(Reg, TRI), Imm);
@@ -122,7 +122,7 @@
case StackMaps::IndirectMemRefOp: {
int64_t Size = (++MOI)->getImm();
assert(Size > 0 && "Need a valid size for indirect memory locations.");
- unsigned Reg = (++MOI)->getReg();
+ Register Reg = (++MOI)->getReg();
int64_t Imm = (++MOI)->getImm();
Locs.emplace_back(StackMaps::Location::Indirect, Size,
getDwarfRegNum(Reg, TRI), Imm);
diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp
index 6e3a5cc..03c68a3 100644
--- a/llvm/lib/CodeGen/TailDuplicator.cpp
+++ b/llvm/lib/CodeGen/TailDuplicator.cpp
@@ -235,8 +235,8 @@
MachineInstr *Copy = Copies[i];
if (!Copy->isCopy())
continue;
- unsigned Dst = Copy->getOperand(0).getReg();
- unsigned Src = Copy->getOperand(1).getReg();
+ Register Dst = Copy->getOperand(0).getReg();
+ Register Src = Copy->getOperand(1).getReg();
if (MRI->hasOneNonDBGUse(Src) &&
MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
// Copy is the only use. Do trivial copy propagation here.
@@ -312,7 +312,7 @@
if (!MI.isPHI())
break;
for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
- unsigned SrcReg = MI.getOperand(i).getReg();
+ Register SrcReg = MI.getOperand(i).getReg();
UsedByPhi->insert(SrcReg);
}
}
@@ -340,17 +340,17 @@
DenseMap<unsigned, RegSubRegPair> &LocalVRMap,
SmallVectorImpl<std::pair<unsigned, RegSubRegPair>> &Copies,
const DenseSet<unsigned> &RegsUsedByPhi, bool Remove) {
- unsigned DefReg = MI->getOperand(0).getReg();
+ Register DefReg = MI->getOperand(0).getReg();
unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB);
assert(SrcOpIdx && "Unable to find matching PHI source?");
- unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
+ Register SrcReg = MI->getOperand(SrcOpIdx).getReg();
unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg();
const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg)));
// Insert a copy from source to the end of the block. The def register is the
// available value liveout of the block.
- unsigned NewDef = MRI->createVirtualRegister(RC);
+ Register NewDef = MRI->createVirtualRegister(RC);
Copies.push_back(std::make_pair(NewDef, RegSubRegPair(SrcReg, SrcSubReg)));
if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
addSSAUpdateEntry(DefReg, NewDef, PredBB);
@@ -384,12 +384,12 @@
MachineOperand &MO = NewMI.getOperand(i);
if (!MO.isReg())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isDef()) {
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
- unsigned NewReg = MRI->createVirtualRegister(RC);
+ Register NewReg = MRI->createVirtualRegister(RC);
MO.setReg(NewReg);
LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
@@ -433,7 +433,7 @@
auto *NewRC = MI->getRegClassConstraint(i, TII, TRI);
if (NewRC == nullptr)
NewRC = OrigRC;
- unsigned NewReg = MRI->createVirtualRegister(NewRC);
+ Register NewReg = MRI->createVirtualRegister(NewRC);
BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(),
TII->get(TargetOpcode::COPY), NewReg)
.addReg(VI->second.Reg, 0, VI->second.SubReg);
@@ -477,7 +477,7 @@
assert(Idx != 0);
MachineOperand &MO0 = MI.getOperand(Idx);
- unsigned Reg = MO0.getReg();
+ Register Reg = MO0.getReg();
if (isDead) {
// Folded into the previous BB.
// There could be duplicate phi source entries. FIXME: Should sdisel
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 1cc2287..e64c67f 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -443,8 +443,8 @@
if (FoldOp.getSubReg() || LiveOp.getSubReg())
return nullptr;
- unsigned FoldReg = FoldOp.getReg();
- unsigned LiveReg = LiveOp.getReg();
+ Register FoldReg = FoldOp.getReg();
+ Register LiveReg = LiveOp.getReg();
assert(Register::isVirtualRegister(FoldReg) && "Cannot fold physregs");
@@ -805,11 +805,11 @@
MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
MachineOperand &OpC = Root.getOperand(0);
- unsigned RegA = OpA.getReg();
- unsigned RegB = OpB.getReg();
- unsigned RegX = OpX.getReg();
- unsigned RegY = OpY.getReg();
- unsigned RegC = OpC.getReg();
+ Register RegA = OpA.getReg();
+ Register RegB = OpB.getReg();
+ Register RegX = OpX.getReg();
+ Register RegY = OpY.getReg();
+ Register RegC = OpC.getReg();
if (Register::isVirtualRegister(RegA))
MRI.constrainRegClass(RegA, RC);
@@ -825,7 +825,7 @@
// Create a new virtual register for the result of (X op Y) instead of
// recycling RegB because the MachineCombiner's computation of the critical
// path requires a new register definition rather than an existing one.
- unsigned NewVR = MRI.createVirtualRegister(RC);
+ Register NewVR = MRI.createVirtualRegister(RC);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
unsigned Opcode = Root.getOpcode();
@@ -887,7 +887,7 @@
// Remat clients assume operand 0 is the defined register.
if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
return false;
- unsigned DefReg = MI.getOperand(0).getReg();
+ Register DefReg = MI.getOperand(0).getReg();
// A sub-register definition can only be rematerialized if the instruction
// doesn't read the other parts of the register. Otherwise it is really a
@@ -924,7 +924,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Reg == 0)
continue;
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index 1952797..ce59452 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -300,7 +300,7 @@
// TODO: The following hack exists because predication passes do not
// correctly append imp-use operands, and readsReg() strangely returns false
// for predicated defs.
- unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
+ Register Reg = DefMI->getOperand(DefOperIdx).getReg();
const MachineFunction &MF = *DefMI->getMF();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 07ffa42..ea97180 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -230,7 +230,7 @@
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg)
continue;
if (MO.isUse() && MOReg != SavedReg)
@@ -299,7 +299,7 @@
MachineOperand &MO = OtherMI.getOperand(i);
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg)
continue;
if (DefReg == MOReg)
@@ -682,7 +682,7 @@
unsigned RegBIdx,
unsigned RegCIdx,
unsigned Dist) {
- unsigned RegC = MI->getOperand(RegCIdx).getReg();
+ Register RegC = MI->getOperand(RegCIdx).getReg();
LLVM_DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
@@ -699,7 +699,7 @@
// Update source register map.
unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
if (FromRegC) {
- unsigned RegA = MI->getOperand(DstIdx).getReg();
+ Register RegA = MI->getOperand(DstIdx).getReg();
SrcRegMap[RegA] = FromRegC;
}
@@ -910,7 +910,7 @@
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg)
continue;
if (MO.isDef())
@@ -954,7 +954,7 @@
for (const MachineOperand &MO : OtherMI.operands()) {
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg)
continue;
if (MO.isDef()) {
@@ -1092,7 +1092,7 @@
for (const MachineOperand &MO : KillMI->operands()) {
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (MO.isUse()) {
if (!MOReg)
continue;
@@ -1129,7 +1129,7 @@
for (const MachineOperand &MO : OtherMI.operands()) {
if (!MO.isReg())
continue;
- unsigned MOReg = MO.getReg();
+ Register MOReg = MO.getReg();
if (!MOReg)
continue;
if (MO.isUse()) {
@@ -1206,8 +1206,8 @@
return false;
bool MadeChange = false;
- unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
- unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
+ Register DstOpReg = MI->getOperand(DstOpIdx).getReg();
+ Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
unsigned OpsNum = MI->getDesc().getNumOperands();
unsigned OtherOpIdx = MI->getDesc().getNumDefs();
for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
@@ -1219,7 +1219,7 @@
!TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
continue;
- unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
+ Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
bool AggressiveCommute = false;
// If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
@@ -1274,8 +1274,8 @@
return false;
MachineInstr &MI = *mi;
- unsigned regA = MI.getOperand(DstIdx).getReg();
- unsigned regB = MI.getOperand(SrcIdx).getReg();
+ Register regA = MI.getOperand(DstIdx).getReg();
+ Register regB = MI.getOperand(SrcIdx).getReg();
assert(Register::isVirtualRegister(regB) &&
"cannot make instruction into two-address form");
@@ -1361,7 +1361,7 @@
const TargetRegisterClass *RC =
TRI->getAllocatableClass(
TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
- unsigned Reg = MRI->createVirtualRegister(RC);
+ Register Reg = MRI->createVirtualRegister(RC);
SmallVector<MachineInstr *, 2> NewMIs;
if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
/*UnfoldLoad=*/true,
@@ -1471,8 +1471,8 @@
AnyOps = true;
MachineOperand &SrcMO = MI->getOperand(SrcIdx);
MachineOperand &DstMO = MI->getOperand(DstIdx);
- unsigned SrcReg = SrcMO.getReg();
- unsigned DstReg = DstMO.getReg();
+ Register SrcReg = SrcMO.getReg();
+ Register DstReg = DstMO.getReg();
// Tied constraint already satisfied?
if (SrcReg == DstReg)
continue;
@@ -1519,7 +1519,7 @@
unsigned DstIdx = TiedPairs[tpi].second;
const MachineOperand &DstMO = MI->getOperand(DstIdx);
- unsigned RegA = DstMO.getReg();
+ Register RegA = DstMO.getReg();
// Grab RegB from the instruction because it may have changed if the
// instruction was commuted.
@@ -1739,8 +1739,8 @@
if (TiedPairs.size() == 1) {
unsigned SrcIdx = TiedPairs[0].first;
unsigned DstIdx = TiedPairs[0].second;
- unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
- unsigned DstReg = mi->getOperand(DstIdx).getReg();
+ Register SrcReg = mi->getOperand(SrcIdx).getReg();
+ Register DstReg = mi->getOperand(DstIdx).getReg();
if (SrcReg != DstReg &&
tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
// The tied operands have been eliminated or shifted further down
@@ -1798,7 +1798,7 @@
void TwoAddressInstructionPass::
eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI;
- unsigned DstReg = MI.getOperand(0).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
if (MI.getOperand(0).getSubReg() || Register::isPhysicalRegister(DstReg) ||
!(MI.getNumOperands() & 1)) {
LLVM_DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
@@ -1815,7 +1815,7 @@
bool DefEmitted = false;
for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
MachineOperand &UseMO = MI.getOperand(i);
- unsigned SrcReg = UseMO.getReg();
+ Register SrcReg = UseMO.getReg();
unsigned SubIdx = MI.getOperand(i+1).getImm();
// Nothing needs to be inserted for undef operands.
if (UseMO.isUndef())
diff --git a/llvm/lib/CodeGen/UnreachableBlockElim.cpp b/llvm/lib/CodeGen/UnreachableBlockElim.cpp
index c534369..de15e6c 100644
--- a/llvm/lib/CodeGen/UnreachableBlockElim.cpp
+++ b/llvm/lib/CodeGen/UnreachableBlockElim.cpp
@@ -173,8 +173,8 @@
if (phi->getNumOperands() == 3) {
const MachineOperand &Input = phi->getOperand(1);
const MachineOperand &Output = phi->getOperand(0);
- unsigned InputReg = Input.getReg();
- unsigned OutputReg = Output.getReg();
+ Register InputReg = Input.getReg();
+ Register OutputReg = Output.getReg();
assert(Output.getSubReg() == 0 && "Cannot have output subregister");
ModifiedPHI = true;