Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
index a4aacfb..30b9c80 100644
--- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp
+++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp
@@ -133,7 +133,7 @@
const TargetRegisterClass *TRC) {
if (!MO.isReg())
return false;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (Register::isVirtualRegister(Reg))
return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
@@ -191,7 +191,7 @@
for (MachineOperand &MO : MI->operands()) {
if ((!MO.isReg()) || (!MO.isUse()))
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
MachineOperand *Op = MI->findRegisterDefOperand(Reg);
@@ -213,7 +213,7 @@
for (MachineOperand &MODef : Def->operands()) {
if ((!MODef.isReg()) || (!MODef.isDef()))
continue;
- unsigned DefReg = MODef.getReg();
+ Register DefReg = MODef.getReg();
if (!Register::isVirtualRegister(DefReg)) {
IsDead = false;
break;
@@ -245,8 +245,8 @@
}
if (MI->isInsertSubreg()) {
- unsigned DPRReg = MI->getOperand(1).getReg();
- unsigned SPRReg = MI->getOperand(2).getReg();
+ Register DPRReg = MI->getOperand(1).getReg();
+ Register SPRReg = MI->getOperand(2).getReg();
if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
@@ -267,7 +267,7 @@
// Find the thing we're subreg copying out of - is it of the same
// regclass as DPRMI? (i.e. a DPR or QPR).
- unsigned FullReg = SPRMI->getOperand(1).getReg();
+ Register FullReg = SPRMI->getOperand(1).getReg();
const TargetRegisterClass *TRC =
MRI->getRegClass(MI->getOperand(1).getReg());
if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
@@ -296,7 +296,7 @@
if (!MI->getOperand(I).isReg())
continue;
++NumTotal;
- unsigned OpReg = MI->getOperand(I).getReg();
+ Register OpReg = MI->getOperand(I).getReg();
if (!Register::isVirtualRegister(OpReg))
break;
@@ -369,7 +369,7 @@
Reached.insert(MI);
if (MI->isPHI()) {
for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
- unsigned Reg = MI->getOperand(I).getReg();
+ Register Reg = MI->getOperand(I).getReg();
if (!Register::isVirtualRegister(Reg)) {
continue;
}
@@ -418,8 +418,8 @@
MachineBasicBlock::iterator InsertBefore,
const DebugLoc &DL, unsigned Reg,
unsigned Lane, bool QPR) {
- unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
- &ARM::DPRRegClass);
+ Register Out =
+ MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass);
BuildMI(MBB, InsertBefore, DL,
TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
.addReg(Reg)
@@ -434,7 +434,7 @@
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
const DebugLoc &DL, unsigned DReg, unsigned Lane,
const TargetRegisterClass *TRC) {
- unsigned Out = MRI->createVirtualRegister(TRC);
+ Register Out = MRI->createVirtualRegister(TRC);
BuildMI(MBB,
InsertBefore,
DL,
@@ -448,7 +448,7 @@
unsigned A15SDOptimizer::createRegSequence(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
- unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
+ Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
BuildMI(MBB,
InsertBefore,
DL,
@@ -466,7 +466,7 @@
MachineBasicBlock::iterator InsertBefore,
const DebugLoc &DL, unsigned Ssub0,
unsigned Ssub1) {
- unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
+ Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
.addReg(Ssub0)
.addReg(Ssub1)
@@ -478,7 +478,7 @@
unsigned A15SDOptimizer::createInsertSubreg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
- unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
+ Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
BuildMI(MBB,
InsertBefore,
DL,
@@ -494,7 +494,7 @@
A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
const DebugLoc &DL) {
- unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
+ Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
BuildMI(MBB,
InsertBefore,
DL,
@@ -622,7 +622,7 @@
// Collect all the uses of this MI's DPR def for updating later.
SmallVector<MachineOperand*, 8> Uses;
- unsigned DPRDefReg = MI->getOperand(0).getReg();
+ Register DPRDefReg = MI->getOperand(0).getReg();
for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
E = MRI->use_end(); I != E; ++I)
Uses.push_back(&*I);