Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
index 70af955..db93b3d 100644
--- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
+++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
@@ -361,7 +361,7 @@
MI->getOpcode() == Mips::SW16_MM))
return false;
- unsigned reg = MI->getOperand(0).getReg();
+ Register reg = MI->getOperand(0).getReg();
if (reg == Mips::RA)
return false;
@@ -403,8 +403,8 @@
if (!GetImm(MI2, 2, Offset2))
return false;
- unsigned Reg1 = MI1->getOperand(0).getReg();
- unsigned Reg2 = MI2->getOperand(0).getReg();
+ Register Reg1 = MI1->getOperand(0).getReg();
+ Register Reg2 = MI2->getOperand(0).getReg();
return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2)));
}
@@ -475,8 +475,8 @@
if (!CheckXWPInstr(MI2, ReduceToLwp, Entry))
return false;
- unsigned Reg1 = MI1->getOperand(1).getReg();
- unsigned Reg2 = MI2->getOperand(1).getReg();
+ Register Reg1 = MI1->getOperand(1).getReg();
+ Register Reg2 = MI2->getOperand(1).getReg();
if (Reg1 != Reg2)
return false;
@@ -621,8 +621,8 @@
MachineInstr *MI1 = Arguments->MI;
MachineInstr *MI2 = &*NextMII;
- unsigned RegDstMI1 = MI1->getOperand(0).getReg();
- unsigned RegSrcMI1 = MI1->getOperand(1).getReg();
+ Register RegDstMI1 = MI1->getOperand(0).getReg();
+ Register RegSrcMI1 = MI1->getOperand(1).getReg();
if (!IsMovepSrcRegister(RegSrcMI1))
return false;
@@ -633,8 +633,8 @@
if (MI2->getOpcode() != Entry.WideOpc())
return false;
- unsigned RegDstMI2 = MI2->getOperand(0).getReg();
- unsigned RegSrcMI2 = MI2->getOperand(1).getReg();
+ Register RegDstMI2 = MI2->getOperand(0).getReg();
+ Register RegSrcMI2 = MI2->getOperand(1).getReg();
if (!IsMovepSrcRegister(RegSrcMI2))
return false;
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index 3ab4f1e..768d54f 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -72,7 +72,7 @@
MachineRegisterInfo &RegInfo = MF.getRegInfo();
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
DebugLoc DL;
- unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
+ Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
V0 = RegInfo.createVirtualRegister(RC);
diff --git a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
index 6d8e5ae..5a5b78c 100644
--- a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
@@ -708,8 +708,8 @@
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
- unsigned regX = MI.getOperand(0).getReg();
- unsigned regY = MI.getOperand(1).getReg();
+ Register regX = MI.getOperand(0).getReg();
+ Register regY = MI.getOperand(1).getReg();
MachineBasicBlock *target = MI.getOperand(2).getMBB();
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
.addReg(regX)
@@ -725,7 +725,7 @@
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
- unsigned regX = MI.getOperand(0).getReg();
+ Register regX = MI.getOperand(0).getReg();
int64_t imm = MI.getOperand(1).getImm();
MachineBasicBlock *target = MI.getOperand(2).getMBB();
unsigned CmpOpc;
@@ -758,9 +758,9 @@
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
- unsigned CC = MI.getOperand(0).getReg();
- unsigned regX = MI.getOperand(1).getReg();
- unsigned regY = MI.getOperand(2).getReg();
+ Register CC = MI.getOperand(0).getReg();
+ Register regX = MI.getOperand(1).getReg();
+ Register regY = MI.getOperand(2).getReg();
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
.addReg(regX)
.addReg(regY);
@@ -777,8 +777,8 @@
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
- unsigned CC = MI.getOperand(0).getReg();
- unsigned regX = MI.getOperand(1).getReg();
+ Register CC = MI.getOperand(0).getReg();
+ Register regX = MI.getOperand(1).getReg();
int64_t Imm = MI.getOperand(2).getImm();
unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index db83fe4..d9e4785 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -376,7 +376,7 @@
void MipsAsmPrinter::emitFrameDirective() {
const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
- unsigned stackReg = RI.getFrameRegister(*MF);
+ Register stackReg = RI.getFrameRegister(*MF);
unsigned returnReg = RI.getRARegister();
unsigned stackSize = MF->getFrameInfo().getStackSize();
@@ -571,7 +571,7 @@
// for 2 for 32 bit mode and 1 for 64 bit mode.
if (NumVals != 2) {
if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
O << '$' << MipsInstPrinter::getRegisterName(Reg);
return false;
}
@@ -597,7 +597,7 @@
const MachineOperand &MO = MI->getOperand(RegOp);
if (!MO.isReg())
return true;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
O << '$' << MipsInstPrinter::getRegisterName(Reg);
return false;
}
diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index 65d84a6..00cd284 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -99,15 +99,15 @@
: (ArePtrs64bit ? Mips::SC64 : Mips::SC);
}
- unsigned Dest = I->getOperand(0).getReg();
- unsigned Ptr = I->getOperand(1).getReg();
- unsigned Mask = I->getOperand(2).getReg();
- unsigned ShiftCmpVal = I->getOperand(3).getReg();
- unsigned Mask2 = I->getOperand(4).getReg();
- unsigned ShiftNewVal = I->getOperand(5).getReg();
- unsigned ShiftAmnt = I->getOperand(6).getReg();
- unsigned Scratch = I->getOperand(7).getReg();
- unsigned Scratch2 = I->getOperand(8).getReg();
+ Register Dest = I->getOperand(0).getReg();
+ Register Ptr = I->getOperand(1).getReg();
+ Register Mask = I->getOperand(2).getReg();
+ Register ShiftCmpVal = I->getOperand(3).getReg();
+ Register Mask2 = I->getOperand(4).getReg();
+ Register ShiftNewVal = I->getOperand(5).getReg();
+ Register ShiftAmnt = I->getOperand(6).getReg();
+ Register Scratch = I->getOperand(7).getReg();
+ Register Scratch2 = I->getOperand(8).getReg();
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB.getBasicBlock();
@@ -240,11 +240,11 @@
MOVE = Mips::OR64;
}
- unsigned Dest = I->getOperand(0).getReg();
- unsigned Ptr = I->getOperand(1).getReg();
- unsigned OldVal = I->getOperand(2).getReg();
- unsigned NewVal = I->getOperand(3).getReg();
- unsigned Scratch = I->getOperand(4).getReg();
+ Register Dest = I->getOperand(0).getReg();
+ Register Ptr = I->getOperand(1).getReg();
+ Register OldVal = I->getOperand(2).getReg();
+ Register NewVal = I->getOperand(3).getReg();
+ Register Scratch = I->getOperand(4).getReg();
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB.getBasicBlock();
@@ -374,15 +374,15 @@
llvm_unreachable("Unknown subword atomic pseudo for expansion!");
}
- unsigned Dest = I->getOperand(0).getReg();
- unsigned Ptr = I->getOperand(1).getReg();
- unsigned Incr = I->getOperand(2).getReg();
- unsigned Mask = I->getOperand(3).getReg();
- unsigned Mask2 = I->getOperand(4).getReg();
- unsigned ShiftAmnt = I->getOperand(5).getReg();
- unsigned OldVal = I->getOperand(6).getReg();
- unsigned BinOpRes = I->getOperand(7).getReg();
- unsigned StoreVal = I->getOperand(8).getReg();
+ Register Dest = I->getOperand(0).getReg();
+ Register Ptr = I->getOperand(1).getReg();
+ Register Incr = I->getOperand(2).getReg();
+ Register Mask = I->getOperand(3).getReg();
+ Register Mask2 = I->getOperand(4).getReg();
+ Register ShiftAmnt = I->getOperand(5).getReg();
+ Register OldVal = I->getOperand(6).getReg();
+ Register BinOpRes = I->getOperand(7).getReg();
+ Register StoreVal = I->getOperand(8).getReg();
const BasicBlock *LLVM_BB = BB.getBasicBlock();
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
@@ -513,10 +513,10 @@
BEQ = Mips::BEQ64;
}
- unsigned OldVal = I->getOperand(0).getReg();
- unsigned Ptr = I->getOperand(1).getReg();
- unsigned Incr = I->getOperand(2).getReg();
- unsigned Scratch = I->getOperand(3).getReg();
+ Register OldVal = I->getOperand(0).getReg();
+ Register Ptr = I->getOperand(1).getReg();
+ Register Incr = I->getOperand(2).getReg();
+ Register Scratch = I->getOperand(3).getReg();
unsigned Opcode = 0;
unsigned OR = 0;
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 702c2b0..80f288a 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -1728,7 +1728,7 @@
return false;
unsigned SrcReg = Reg + VA.getValNo();
- unsigned DestReg = VA.getLocReg();
+ Register DestReg = VA.getLocReg();
// Avoid a cross-class copy. This is very unlikely.
if (!MRI.getRegClass(SrcReg)->contains(DestReg))
return false;
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 9ba54d6..42d158f 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -65,7 +65,7 @@
/// getGlobalBaseReg - Output the instructions required to put the
/// GOT address into a register.
SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
- unsigned GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
+ Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
return CurDAG->getRegister(GlobalBaseReg, getTargetLowering()->getPointerTy(
CurDAG->getDataLayout()))
.getNode();
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 0ff0900..6e86d94 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -1257,7 +1257,7 @@
static unsigned
addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
{
- unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
+ Register VReg = MF.getRegInfo().createVirtualRegister(RC);
MF.getRegInfo().addLiveIn(PReg, VReg);
return VReg;
}
@@ -1477,10 +1477,10 @@
llvm_unreachable("Unknown pseudo atomic for replacement!");
}
- unsigned OldVal = MI.getOperand(0).getReg();
- unsigned Ptr = MI.getOperand(1).getReg();
- unsigned Incr = MI.getOperand(2).getReg();
- unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
+ Register OldVal = MI.getOperand(0).getReg();
+ Register Ptr = MI.getOperand(1).getReg();
+ Register Incr = MI.getOperand(2).getReg();
+ Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
MachineBasicBlock::iterator II(MI);
@@ -1519,8 +1519,8 @@
// containing the word.
//
- unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
- unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
+ Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
+ Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
@@ -1556,7 +1556,7 @@
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
- unsigned ScrReg = RegInfo.createVirtualRegister(RC);
+ Register ScrReg = RegInfo.createVirtualRegister(RC);
assert(Size < 32);
int64_t ShiftImm = 32 - (Size * 8);
@@ -1581,21 +1581,21 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Dest = MI.getOperand(0).getReg();
- unsigned Ptr = MI.getOperand(1).getReg();
- unsigned Incr = MI.getOperand(2).getReg();
+ Register Dest = MI.getOperand(0).getReg();
+ Register Ptr = MI.getOperand(1).getReg();
+ Register Incr = MI.getOperand(2).getReg();
- unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
- unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
- unsigned Mask = RegInfo.createVirtualRegister(RC);
- unsigned Mask2 = RegInfo.createVirtualRegister(RC);
- unsigned Incr2 = RegInfo.createVirtualRegister(RC);
- unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
- unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
- unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
- unsigned Scratch = RegInfo.createVirtualRegister(RC);
- unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
- unsigned Scratch3 = RegInfo.createVirtualRegister(RC);
+ Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
+ Register ShiftAmt = RegInfo.createVirtualRegister(RC);
+ Register Mask = RegInfo.createVirtualRegister(RC);
+ Register Mask2 = RegInfo.createVirtualRegister(RC);
+ Register Incr2 = RegInfo.createVirtualRegister(RC);
+ Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
+ Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
+ Register MaskUpper = RegInfo.createVirtualRegister(RC);
+ Register Scratch = RegInfo.createVirtualRegister(RC);
+ Register Scratch2 = RegInfo.createVirtualRegister(RC);
+ Register Scratch3 = RegInfo.createVirtualRegister(RC);
unsigned AtomicOp = 0;
switch (MI.getOpcode()) {
@@ -1678,7 +1678,7 @@
if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
- unsigned Off = RegInfo.createVirtualRegister(RC);
+ Register Off = RegInfo.createVirtualRegister(RC);
BuildMI(BB, DL, TII->get(Mips::XORi), Off)
.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
@@ -1738,12 +1738,12 @@
unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
: Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
- unsigned Dest = MI.getOperand(0).getReg();
- unsigned Ptr = MI.getOperand(1).getReg();
- unsigned OldVal = MI.getOperand(2).getReg();
- unsigned NewVal = MI.getOperand(3).getReg();
+ Register Dest = MI.getOperand(0).getReg();
+ Register Ptr = MI.getOperand(1).getReg();
+ Register OldVal = MI.getOperand(2).getReg();
+ Register NewVal = MI.getOperand(3).getReg();
- unsigned Scratch = MRI.createVirtualRegister(RC);
+ Register Scratch = MRI.createVirtualRegister(RC);
MachineBasicBlock::iterator II(MI);
// We need to create copies of the various registers and kill them at the
@@ -1751,9 +1751,9 @@
// after fast register allocation, the spills will end up outside of the
// blocks that their values are defined in, causing livein errors.
- unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
- unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
- unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
+ Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
+ Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
+ Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
@@ -1790,22 +1790,22 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Dest = MI.getOperand(0).getReg();
- unsigned Ptr = MI.getOperand(1).getReg();
- unsigned CmpVal = MI.getOperand(2).getReg();
- unsigned NewVal = MI.getOperand(3).getReg();
+ Register Dest = MI.getOperand(0).getReg();
+ Register Ptr = MI.getOperand(1).getReg();
+ Register CmpVal = MI.getOperand(2).getReg();
+ Register NewVal = MI.getOperand(3).getReg();
- unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
- unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
- unsigned Mask = RegInfo.createVirtualRegister(RC);
- unsigned Mask2 = RegInfo.createVirtualRegister(RC);
- unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
- unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
- unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
- unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
- unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
- unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
- unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
+ Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
+ Register ShiftAmt = RegInfo.createVirtualRegister(RC);
+ Register Mask = RegInfo.createVirtualRegister(RC);
+ Register Mask2 = RegInfo.createVirtualRegister(RC);
+ Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
+ Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
+ Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
+ Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
+ Register MaskUpper = RegInfo.createVirtualRegister(RC);
+ Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
+ Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
: Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
@@ -1820,8 +1820,8 @@
// value isn't a problem.
// The Dead flag is needed as the value in scratch isn't used by any other
// instruction. Kill isn't used as Dead is more precise.
- unsigned Scratch = RegInfo.createVirtualRegister(RC);
- unsigned Scratch2 = RegInfo.createVirtualRegister(RC);
+ Register Scratch = RegInfo.createVirtualRegister(RC);
+ Register Scratch2 = RegInfo.createVirtualRegister(RC);
// insert new blocks after the current block
const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -1859,7 +1859,7 @@
if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
- unsigned Off = RegInfo.createVirtualRegister(RC);
+ Register Off = RegInfo.createVirtualRegister(RC);
BuildMI(BB, DL, TII->get(Mips::XORi), Off)
.addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
@@ -3167,7 +3167,7 @@
Arg, DAG.getConstant(1, DL, MVT::i32));
if (!Subtarget.isLittle())
std::swap(Lo, Hi);
- unsigned LocRegLo = VA.getLocReg();
+ Register LocRegLo = VA.getLocReg();
unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
@@ -3523,7 +3523,7 @@
// Arguments stored on registers
if (IsRegLoc) {
MVT RegVT = VA.getLocVT();
- unsigned ArgReg = VA.getLocReg();
+ Register ArgReg = VA.getLocReg();
const TargetRegisterClass *RC = getRegClassFor(RegVT);
// Transform the arguments stored on
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 8426579..da31926 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -503,7 +503,7 @@
Opcode = Mips::TRUNC_W_S;
else
Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
- unsigned ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
+ Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
.addDef(ResultInFPR)
.addUse(I.getOperand(1).getReg());
@@ -724,7 +724,7 @@
// MipsFCMPCondCode, result is inverted i.e. MOVT_I is used.
unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I;
- unsigned TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
.addDef(TrueInReg)
.addUse(Mips::ZERO)
diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
index c3853e7..8bd64ff 100644
--- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
@@ -151,7 +151,7 @@
MachineBasicBlock::iterator I) {
MachineFunction &MF = *MBB->getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
- unsigned SrcReg = I->getOperand(0).getReg();
+ Register SrcReg = I->getOperand(0).getReg();
unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
.addReg(SrcReg);
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index 4c6cc1e..55efe2c 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -171,8 +171,8 @@
assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
const TargetRegisterClass *RC = RegInfo.intRegClass(4);
- unsigned VR = MRI.createVirtualRegister(RC);
- unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+ Register VR = MRI.createVirtualRegister(RC);
+ Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
@@ -186,8 +186,8 @@
assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
const TargetRegisterClass *RC = RegInfo.intRegClass(4);
- unsigned VR = MRI.createVirtualRegister(RC);
- unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+ Register VR = MRI.createVirtualRegister(RC);
+ Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
.addReg(Src, getKillRegState(I->getOperand(0).isKill()));
@@ -204,11 +204,11 @@
assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
- unsigned VR0 = MRI.createVirtualRegister(RC);
- unsigned VR1 = MRI.createVirtualRegister(RC);
- unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
- unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
- unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
+ Register VR0 = MRI.createVirtualRegister(RC);
+ Register VR1 = MRI.createVirtualRegister(RC);
+ Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+ Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
+ Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
DebugLoc DL = I->getDebugLoc();
const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
@@ -229,9 +229,9 @@
assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
- unsigned VR0 = MRI.createVirtualRegister(RC);
- unsigned VR1 = MRI.createVirtualRegister(RC);
- unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+ Register VR0 = MRI.createVirtualRegister(RC);
+ Register VR1 = MRI.createVirtualRegister(RC);
+ Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
DebugLoc DL = I->getDebugLoc();
@@ -242,7 +242,7 @@
}
bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
- unsigned Src = I->getOperand(1).getReg();
+ Register Src = I->getOperand(1).getReg();
std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
if (!Opcodes.first)
@@ -262,11 +262,11 @@
const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);
unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;
const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
- unsigned VR0 = MRI.createVirtualRegister(RC);
- unsigned VR1 = MRI.createVirtualRegister(RC);
+ Register VR0 = MRI.createVirtualRegister(RC);
+ Register VR1 = MRI.createVirtualRegister(RC);
unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
- unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
- unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
+ Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
+ Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
DebugLoc DL = I->getDebugLoc();
BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
@@ -304,9 +304,9 @@
// stack is used.
if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
&& I->getOperand(3).getReg() == Mips::SP) {
- unsigned DstReg = I->getOperand(0).getReg();
- unsigned LoReg = I->getOperand(1).getReg();
- unsigned HiReg = I->getOperand(2).getReg();
+ Register DstReg = I->getOperand(0).getReg();
+ Register LoReg = I->getOperand(1).getReg();
+ Register HiReg = I->getOperand(2).getReg();
// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
// the cases where mthc1 is not available). 64-bit architectures and
@@ -346,7 +346,7 @@
const MachineOperand &Op2 = I->getOperand(2);
if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
- unsigned DstReg = I->getOperand(0).getReg();
+ Register DstReg = I->getOperand(0).getReg();
BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
return true;
}
@@ -369,8 +369,8 @@
// stack is used.
if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
&& I->getOperand(3).getReg() == Mips::SP) {
- unsigned DstReg = I->getOperand(0).getReg();
- unsigned SrcReg = Op1.getReg();
+ Register DstReg = I->getOperand(0).getReg();
+ Register SrcReg = Op1.getReg();
unsigned N = Op2.getImm();
int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
@@ -538,7 +538,7 @@
if (RegInfo.needsStackRealignment(MF)) {
// addiu $Reg, $zero, -MaxAlignment
// andi $sp, $sp, $Reg
- unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
+ Register VR = MF.getRegInfo().createVirtualRegister(RC);
assert(isInt<16>(MFI.getMaxAlignment()) &&
"Function's alignment size requirement is not supported.");
int MaxAlign = -(int)MFI.getMaxAlignment();
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index edf57a3..bf7e7b6 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -3062,13 +3062,13 @@
BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
// Fill $FBB.
- unsigned VR2 = RegInfo.createVirtualRegister(RC);
+ Register VR2 = RegInfo.createVirtualRegister(RC);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
.addReg(Mips::ZERO).addImm(0);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
// Fill $TBB.
- unsigned VR1 = RegInfo.createVirtualRegister(RC);
+ Register VR1 = RegInfo.createVirtualRegister(RC);
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
.addReg(Mips::ZERO).addImm(1);
@@ -3131,13 +3131,13 @@
.addMBB(TBB);
// Fill $FBB.
- unsigned RD1 = RegInfo.createVirtualRegister(RC);
+ Register RD1 = RegInfo.createVirtualRegister(RC);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
.addReg(Mips::ZERO).addImm(0);
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
// Fill $TBB.
- unsigned RD2 = RegInfo.createVirtualRegister(RC);
+ Register RD2 = RegInfo.createVirtualRegister(RC);
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
.addReg(Mips::ZERO).addImm(1);
@@ -3169,8 +3169,8 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Fd = MI.getOperand(0).getReg();
- unsigned Ws = MI.getOperand(1).getReg();
+ Register Fd = MI.getOperand(0).getReg();
+ Register Ws = MI.getOperand(1).getReg();
unsigned Lane = MI.getOperand(2).getImm();
if (Lane == 0) {
@@ -3185,9 +3185,9 @@
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
} else {
- unsigned Wt = RegInfo.createVirtualRegister(
- Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
- &Mips::MSA128WEvensRegClass);
+ Register Wt = RegInfo.createVirtualRegister(
+ Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
+ : &Mips::MSA128WEvensRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
@@ -3214,15 +3214,15 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
- unsigned Fd = MI.getOperand(0).getReg();
- unsigned Ws = MI.getOperand(1).getReg();
+ Register Fd = MI.getOperand(0).getReg();
+ Register Ws = MI.getOperand(1).getReg();
unsigned Lane = MI.getOperand(2).getImm() * 2;
DebugLoc DL = MI.getDebugLoc();
if (Lane == 0)
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
else {
- unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
+ Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
@@ -3244,13 +3244,13 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
- unsigned Wd_in = MI.getOperand(1).getReg();
+ Register Wd = MI.getOperand(0).getReg();
+ Register Wd_in = MI.getOperand(1).getReg();
unsigned Lane = MI.getOperand(2).getImm();
- unsigned Fs = MI.getOperand(3).getReg();
- unsigned Wt = RegInfo.createVirtualRegister(
- Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
- &Mips::MSA128WEvensRegClass);
+ Register Fs = MI.getOperand(3).getReg();
+ Register Wt = RegInfo.createVirtualRegister(
+ Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
+ : &Mips::MSA128WEvensRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
.addImm(0)
@@ -3280,11 +3280,11 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
- unsigned Wd_in = MI.getOperand(1).getReg();
+ Register Wd = MI.getOperand(0).getReg();
+ Register Wd_in = MI.getOperand(1).getReg();
unsigned Lane = MI.getOperand(2).getImm();
- unsigned Fs = MI.getOperand(3).getReg();
- unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
+ Register Fs = MI.getOperand(3).getReg();
+ Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
.addImm(0)
@@ -3326,10 +3326,10 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
- unsigned SrcVecReg = MI.getOperand(1).getReg();
- unsigned LaneReg = MI.getOperand(2).getReg();
- unsigned SrcValReg = MI.getOperand(3).getReg();
+ Register Wd = MI.getOperand(0).getReg();
+ Register SrcVecReg = MI.getOperand(1).getReg();
+ Register LaneReg = MI.getOperand(2).getReg();
+ Register SrcValReg = MI.getOperand(3).getReg();
const TargetRegisterClass *VecRC = nullptr;
// FIXME: This should be true for N32 too.
@@ -3370,7 +3370,7 @@
}
if (IsFP) {
- unsigned Wt = RegInfo.createVirtualRegister(VecRC);
+ Register Wt = RegInfo.createVirtualRegister(VecRC);
BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
.addImm(0)
.addReg(SrcValReg)
@@ -3380,7 +3380,7 @@
// Convert the lane index into a byte index
if (EltSizeInBytes != 1) {
- unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
+ Register LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
.addReg(LaneReg)
.addImm(EltLog2Size);
@@ -3388,13 +3388,13 @@
}
// Rotate bytes around so that the desired lane is element zero
- unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
+ Register WdTmp1 = RegInfo.createVirtualRegister(VecRC);
BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
.addReg(SrcVecReg)
.addReg(SrcVecReg)
.addReg(LaneReg, 0, SubRegIdx);
- unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
+ Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
if (IsFP) {
// Use insve.df to insert to element zero
BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
@@ -3413,7 +3413,7 @@
// Rotate elements the rest of the way for a full rotation.
// sld.df inteprets $rt modulo the number of columns so we only need to negate
// the lane index to do this.
- unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
+ Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
LaneTmp2)
.addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
@@ -3440,12 +3440,12 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
- unsigned Fs = MI.getOperand(1).getReg();
- unsigned Wt1 = RegInfo.createVirtualRegister(
+ Register Wd = MI.getOperand(0).getReg();
+ Register Fs = MI.getOperand(1).getReg();
+ Register Wt1 = RegInfo.createVirtualRegister(
Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
: &Mips::MSA128WEvensRegClass);
- unsigned Wt2 = RegInfo.createVirtualRegister(
+ Register Wt2 = RegInfo.createVirtualRegister(
Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
: &Mips::MSA128WEvensRegClass);
@@ -3475,10 +3475,10 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
- unsigned Fs = MI.getOperand(1).getReg();
- unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
- unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
+ Register Wd = MI.getOperand(0).getReg();
+ Register Fs = MI.getOperand(1).getReg();
+ Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
+ Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
@@ -3509,8 +3509,8 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Ws = MI.getOperand(0).getReg();
- unsigned Rt = MI.getOperand(1).getReg();
+ Register Ws = MI.getOperand(0).getReg();
+ Register Rt = MI.getOperand(1).getReg();
const MachineMemOperand &MMO = **MI.memoperands_begin();
unsigned Imm = MMO.getOffset();
@@ -3522,11 +3522,11 @@
: (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
: &Mips::GPR64RegClass);
const bool UsingMips32 = RC == &Mips::GPR32RegClass;
- unsigned Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
+ Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
if(!UsingMips32) {
- unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+ Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
.addImm(0)
.addReg(Rs)
@@ -3564,7 +3564,7 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
+ Register Wd = MI.getOperand(0).getReg();
// Caution: A load via the GOT can expand to a GPR32 operand, a load via
// spill and reload can expand as a GPR64 operand. Examine the
@@ -3575,7 +3575,7 @@
: &Mips::GPR64RegClass);
const bool UsingMips32 = RC == &Mips::GPR32RegClass;
- unsigned Rt = RegInfo.createVirtualRegister(RC);
+ Register Rt = RegInfo.createVirtualRegister(RC);
MachineInstrBuilder MIB =
BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
@@ -3583,7 +3583,7 @@
MIB.add(MI.getOperand(i));
if(!UsingMips32) {
- unsigned Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
+ Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
Rt = Tmp;
}
@@ -3658,11 +3658,11 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- unsigned Wd = MI.getOperand(0).getReg();
- unsigned Fs = MI.getOperand(1).getReg();
+ Register Wd = MI.getOperand(0).getReg();
+ Register Fs = MI.getOperand(1).getReg();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
- unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
+ Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
const TargetRegisterClass *GPRRC =
IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
unsigned MFC1Opc = IsFGR64onMips64
@@ -3671,16 +3671,16 @@
unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
// Perform the register class copy as mentioned above.
- unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
+ Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
unsigned WPHI = Wtemp;
if (IsFGR64onMips32) {
- unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
+ Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
- unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
- unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
+ Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
+ Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
.addReg(Wtemp)
.addReg(Rtemp2)
@@ -3693,7 +3693,7 @@
}
if (IsFGR64) {
- unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
+ Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
.addReg(WPHI)
.addReg(WPHI);
@@ -3817,8 +3817,8 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
- unsigned Ws1 = RegInfo.createVirtualRegister(RC);
- unsigned Ws2 = RegInfo.createVirtualRegister(RC);
+ Register Ws1 = RegInfo.createVirtualRegister(RC);
+ Register Ws2 = RegInfo.createVirtualRegister(RC);
DebugLoc DL = MI.getDebugLoc();
// Splat 1.0 into a vector
@@ -3846,8 +3846,8 @@
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
- unsigned Ws1 = RegInfo.createVirtualRegister(RC);
- unsigned Ws2 = RegInfo.createVirtualRegister(RC);
+ Register Ws1 = RegInfo.createVirtualRegister(RC);
+ Register Ws2 = RegInfo.createVirtualRegister(RC);
DebugLoc DL = MI.getDebugLoc();
// Splat 1.0 into a vector
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 4e49f5e..2126a1b 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -628,7 +628,7 @@
// The first instruction can be a LUi, which is different from other
// instructions (ADDiu, ORI and SLL) in that it does not have a register
// operand.
- unsigned Reg = RegInfo.createVirtualRegister(RC);
+ Register Reg = RegInfo.createVirtualRegister(RC);
if (Inst->Opc == LUi)
BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
@@ -734,9 +734,9 @@
// Add lo/hi registers if the mtlo/hi instructions created have explicit
// def registers.
if (HasExplicitDef) {
- unsigned DstReg = I->getOperand(0).getReg();
- unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
- unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
+ Register DstReg = I->getOperand(0).getReg();
+ Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
+ Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
LoInst.addReg(DstLo, RegState::Define);
HiInst.addReg(DstHi, RegState::Define);
}
@@ -773,14 +773,14 @@
MachineBasicBlock::iterator I,
bool isMicroMips,
bool FP64) const {
- unsigned DstReg = I->getOperand(0).getReg();
- unsigned SrcReg = I->getOperand(1).getReg();
+ Register DstReg = I->getOperand(0).getReg();
+ Register SrcReg = I->getOperand(1).getReg();
unsigned N = I->getOperand(2).getImm();
DebugLoc dl = I->getDebugLoc();
assert(N < 2 && "Invalid immediate");
unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
- unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
+ Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
// FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
// in MipsSEFrameLowering.cpp.
@@ -815,7 +815,7 @@
void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
bool isMicroMips, bool FP64) const {
- unsigned DstReg = I->getOperand(0).getReg();
+ Register DstReg = I->getOperand(0).getReg();
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc();
@@ -883,8 +883,8 @@
unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
- unsigned OffsetReg = I->getOperand(0).getReg();
- unsigned TargetReg = I->getOperand(1).getReg();
+ Register OffsetReg = I->getOperand(0).getReg();
+ Register TargetReg = I->getOperand(1).getReg();
// addu $ra, $v0, $zero
// addu $sp, $sp, $v1
diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
index f4b164d..370150b 100644
--- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
@@ -224,7 +224,7 @@
const TargetRegisterClass *PtrRC =
ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
- unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
+ Register Reg = RegInfo.createVirtualRegister(PtrRC);
const MipsSEInstrInfo &TII =
*static_cast<const MipsSEInstrInfo *>(
MBB.getParent()->getSubtarget().getInstrInfo());