commit 0d11212f004c9193dd1cb2b01a80d6934b5fb5f9
author Krzysztof Parzyszek <kparzysz@codeaurora.org> Thu Jan 14 21:59:22 2016 +0000
committer Krzysztof Parzyszek <kparzysz@codeaurora.org> Thu Jan 14 21:59:22 2016 +0000
tree 986c25e8fbf9c50e753d7cf977f947191ae7b71e
parent 80c0974c6bc690f7087693f1704747e664d06d1a

[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword

llvm-svn: 257815

llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index ab28120..8ded94d 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1966,11 +1966,10 @@
     NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
     BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
         .addReg(L.Reg, 0, L.Sub);
-  } else if (!L.Low && Opc != Hexagon::S2_extractu) {
+  } else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
     NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
-    BuildMI(B, MI, DL, HII.get(Hexagon::S2_extractu), NewR)
+    BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
         .addReg(L.Reg, 0, L.Sub)
-        .addImm(16)
         .addImm(16);
   }
   if (NewR == 0)