diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
index ceb6fc5..1086242 100644
--- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -181,19 +181,19 @@
 /// operand requires relocation, record the relocation and return zero.
 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
                                            const MachineOperand &MO) {
-  if (MO.isRegister())
+  if (MO.isReg())
     return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
-  else if (MO.isImmediate())
+  else if (MO.isImm())
     return static_cast<unsigned>(MO.getImm());
-  else if (MO.isGlobalAddress())
+  else if (MO.isGlobal())
     emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, false);
-  else if (MO.isExternalSymbol())
+  else if (MO.isSymbol())
     emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
-  else if (MO.isConstantPoolIndex())
+  else if (MO.isCPI())
     emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
-  else if (MO.isJumpTableIndex())
+  else if (MO.isJTI())
     emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
-  else if (MO.isMachineBasicBlock())
+  else if (MO.isMBB())
     emitMachineBasicBlock(MO.getMBB());
   else {
     cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
@@ -351,7 +351,7 @@
                                           const TargetInstrDesc &TID) const {
   for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
     const MachineOperand &MO = MI.getOperand(i-1);
-    if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
+    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
       return 1 << ARMII::S_BitShift;
   }
   return 0;
@@ -414,7 +414,7 @@
     return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
 
   const MachineOperand &MO = MI.getOperand(OpIdx);
-  if (MO.isRegister())
+  if (MO.isReg())
     // Encode register Rm.
     return Binary | getMachineOpValue(MI, NumDefs + 1);
 
@@ -538,7 +538,7 @@
   // Set registers
   for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI.getOperand(i);
-    if (MO.isRegister() && MO.isImplicit())
+    if (MO.isReg() && MO.isImplicit())
       continue;
     unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
     assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 3ddffde..5d13847 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -416,7 +416,7 @@
 
       // Scan the instructions for constant pool operands.
       for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
-        if (I->getOperand(op).isConstantPoolIndex()) {
+        if (I->getOperand(op).isCPI()) {
           // We found one.  The addressing mode tells us the max displacement
           // from the PC that this instruction permits.
           
@@ -818,7 +818,7 @@
       U.CPEMI = CPEs[i].CPEMI;
       // Change the CPI in the instruction operand to refer to the clone.
       for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
-        if (UserMI->getOperand(j).isConstantPoolIndex()) {
+        if (UserMI->getOperand(j).isCPI()) {
           UserMI->getOperand(j).setIndex(CPEs[i].CPI);
           break;
         }
@@ -1058,7 +1058,7 @@
   
   // Finally, change the CPI in the instruction operand to be ID.
   for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
-    if (UserMI->getOperand(i).isConstantPoolIndex()) {
+    if (UserMI->getOperand(i).isCPI()) {
       UserMI->getOperand(i).setIndex(ID);
       break;
     }
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 839ee6a..e1f44bd 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -64,8 +64,8 @@
   case ARM::MOVr:
   case ARM::tMOVr:
     assert(MI.getDesc().getNumOperands() >= 2 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
            "Invalid ARM MOV instruction");
     SrcReg = MI.getOperand(1).getReg();
     DstReg = MI.getOperand(0).getReg();
@@ -77,9 +77,9 @@
   switch (MI->getOpcode()) {
   default: break;
   case ARM::LDR:
-    if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isRegister() &&
-        MI->getOperand(3).isImmediate() && 
+    if (MI->getOperand(1).isFI() &&
+        MI->getOperand(2).isReg() &&
+        MI->getOperand(3).isImm() &&
         MI->getOperand(2).getReg() == 0 &&
         MI->getOperand(3).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
@@ -88,16 +88,16 @@
     break;
   case ARM::FLDD:
   case ARM::FLDS:
-    if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isImmediate() && 
+    if (MI->getOperand(1).isFI() &&
+        MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
     break;
   case ARM::tRestore:
-    if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isImmediate() && 
+    if (MI->getOperand(1).isFI() &&
+        MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
@@ -111,9 +111,9 @@
   switch (MI->getOpcode()) {
   default: break;
   case ARM::STR:
-    if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isRegister() &&
-        MI->getOperand(3).isImmediate() && 
+    if (MI->getOperand(1).isFI() &&
+        MI->getOperand(2).isReg() &&
+        MI->getOperand(3).isImm() &&
         MI->getOperand(2).getReg() == 0 &&
         MI->getOperand(3).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
@@ -122,16 +122,16 @@
     break;
   case ARM::FSTD:
   case ARM::FSTS:
-    if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isImmediate() && 
+    if (MI->getOperand(1).isFI() &&
+        MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
     break;
   case ARM::tSpill:
-    if (MI->getOperand(1).isFrameIndex() &&
-        MI->getOperand(2).isImmediate() && 
+    if (MI->getOperand(1).isFI() &&
+        MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
@@ -298,7 +298,7 @@
   // Transfer LiveVariables states, kill / dead info.
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isRegister() && MO.getReg() &&
+    if (MO.isReg() && MO.getReg() &&
         TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
       unsigned Reg = MO.getReg();
       
@@ -491,11 +491,11 @@
 
 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
                                                      MachineOperand &MO) {
-  if (MO.isRegister())
+  if (MO.isReg())
     MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
-  else if (MO.isImmediate())
+  else if (MO.isImm())
     MIB = MIB.addImm(MO.getImm());
-  else if (MO.isFrameIndex())
+  else if (MO.isFI())
     MIB = MIB.addFrameIndex(MO.getIndex());
   else
     assert(0 && "Unknown operand for ARMInstrAddOperand!");
@@ -538,7 +538,7 @@
   if (RC == ARM::GPRRegisterClass) {
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     if (AFI->isThumbFunction()) {
-      Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
+      Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
       MachineInstrBuilder MIB = 
         BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
       for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -594,7 +594,7 @@
   if (RC == ARM::GPRRegisterClass) {
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     if (AFI->isThumbFunction()) {
-      Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
+      Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
       MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
       for (unsigned i = 0, e = Addr.size(); i != e; ++i)
         MIB = ARMInstrAddOperand(MIB, Addr[i]);
@@ -868,7 +868,7 @@
   bool Found = false;
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
+    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
       Pred.push_back(MO);
       Found = true;
     }
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 8bd4caa..27fec1f 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -544,13 +544,13 @@
   default: break;
   case ARM::LDR:
   case ARM::STR:
-    return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
+    return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
   case ARM::FLDS:
   case ARM::FSTS:
-    return MI->getOperand(1).isRegister();
+    return MI->getOperand(1).isReg();
   case ARM::FLDD:
   case ARM::FSTD:
-    return MI->getOperand(1).isRegister();
+    return MI->getOperand(1).isReg();
   }
   return false;
 }
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index 3a0a57d..2091899 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -540,7 +540,7 @@
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   bool isThumb = AFI->isThumbFunction();
 
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
@@ -1020,7 +1020,7 @@
       for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
         for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
           for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
-            if (I->getOperand(i).isFrameIndex()) {
+            if (I->getOperand(i).isFI()) {
               unsigned Opcode = I->getOpcode();
               const TargetInstrDesc &Desc = TII.get(Opcode);
               unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
@@ -1086,7 +1086,7 @@
                                    int Opc, unsigned Area,
                                    const ARMSubtarget &STI) {
   while (MBBI != MBB.end() &&
-         MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
+         MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
     if (Area != 0) {
       bool Done = false;
       unsigned Category = 0;
@@ -1250,7 +1250,7 @@
   return ((MI->getOpcode() == ARM::FLDD ||
            MI->getOpcode() == ARM::LDR  ||
            MI->getOpcode() == ARM::tRestore) &&
-          MI->getOperand(1).isFrameIndex() &&
+          MI->getOperand(1).isFI() &&
           isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
 }
 
diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 8789b82..62bf87b 100644
--- a/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -359,7 +359,7 @@
 /// immediate in bits 0-7.
 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
   const MachineOperand &MO = MI->getOperand(OpNum);
-  assert(MO.isImmediate() && "Not a valid so_imm value!");
+  assert(MO.isImm() && "Not a valid so_imm value!");
   printSOImm(O, MO.getImm(), TAI);
 }
 
@@ -367,7 +367,7 @@
 /// followed by a or to materialize.
 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
   const MachineOperand &MO = MI->getOperand(OpNum);
-  assert(MO.isImmediate() && "Not a valid so_imm value!");
+  assert(MO.isImm() && "Not a valid so_imm value!");
   unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
   unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
   printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
@@ -413,7 +413,7 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
   const MachineOperand &MO3 = MI->getOperand(Op+2);
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
@@ -526,7 +526,7 @@
   const MachineOperand &MO1 = MI->getOperand(Op);
   const MachineOperand &MO2 = MI->getOperand(Op+1);
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
@@ -587,7 +587,7 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
   const MachineOperand &MO3 = MI->getOperand(Op+2);
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
@@ -749,9 +749,9 @@
       // Fallthrough
     case 'H': // Write second word of DI / DF reference.  
       // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNo).isRegister() ||
+      if (!MI->getOperand(OpNo).isReg() ||
           OpNo+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNo+1).isRegister())
+          !MI->getOperand(OpNo+1).isReg())
         return true;
       ++OpNo;   // Return the high-part.
     }
diff --git a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 9a4102c..5fb6918 100644
--- a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -80,7 +80,7 @@
     assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            "Not physreg??");
     O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
-  } else if (MO.isImmediate()) {
+  } else if (MO.isImm()) {
     O << MO.getImm();
     assert(MO.getImm() < (1 << 30));
   } else {
diff --git a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
index b514409..0d44114 100644
--- a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -148,12 +148,11 @@
   unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
                    // or things that get fixed up later by the JIT.
 
-  if (MO.isRegister()) {
+  if (MO.isReg()) {
     rv = getAlphaRegNumber(MO.getReg());
-  } else if (MO.isImmediate()) {
+  } else if (MO.isImm()) {
     rv = MO.getImm();
-  } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
-             || MO.isConstantPoolIndex()) {
+  } else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
     DOUT << MO << " is a relocated op for " << MI << "\n";
     unsigned Reloc = 0;
     int Offset = 0;
@@ -193,19 +192,19 @@
       assert(0 && "unknown relocatable instruction");
       abort();
     }
-    if (MO.isGlobalAddress())
+    if (MO.isGlobal())
       MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
                                                  Reloc, MO.getGlobal(), Offset,
                                                  isa<Function>(MO.getGlobal()),
                                                  useGOT));
-    else if (MO.isExternalSymbol())
+    else if (MO.isSymbol())
       MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
                                                      Reloc, MO.getSymbolName(),
                                                      Offset, true));
     else
      MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
                                           Reloc, MO.getIndex(), Offset));
-  } else if (MO.isMachineBasicBlock()) {
+  } else if (MO.isMBB()) {
     MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
                                                Alpha::reloc_bsr, MO.getMBB()));
   }else {
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index b566de4..7f3b32f 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -35,9 +35,9 @@
     // or r1, r2, r2 
     // cpys(s|t) r1 r2 r2
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isReg() &&
            "invalid Alpha BIS instruction!");
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       sourceReg = MI.getOperand(1).getReg();
@@ -57,7 +57,7 @@
   case Alpha::LDWU:
   case Alpha::LDS:
   case Alpha::LDT:
-    if (MI->getOperand(1).isFrameIndex()) {
+    if (MI->getOperand(1).isFI()) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -75,7 +75,7 @@
   case Alpha::STW:
   case Alpha::STS:
   case Alpha::STT:
-    if (MI->getOperand(1).isFrameIndex()) {
+    if (MI->getOperand(1).isFI()) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -200,7 +200,7 @@
     BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
     else
       MIB.addImm(MO.getImm());
@@ -245,7 +245,7 @@
     BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
     else
       MIB.addImm(MO.getImm());
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index dd8460a..3523b26 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -159,7 +159,7 @@
   MachineFunction &MF = *MBB.getParent();
   bool FP = hasFP(MF);
 
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
diff --git a/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp b/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp
index 8d9e891..c43ca0d6 100644
--- a/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp
+++ b/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp
@@ -81,10 +81,10 @@
 
     void printOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.isRegister()) {
+      if (MO.isReg()) {
         assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
         O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
-      } else if (MO.isImmediate()) {
+      } else if (MO.isImm()) {
         O << MO.getImm();
       } else {
         printOp(MO);
@@ -186,8 +186,8 @@
     printMemRegImmS10(const MachineInstr *MI, unsigned OpNo)
     {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      assert(MO.isImmediate()
-             && "printMemRegImmS10 first operand is not immedate");
+      assert(MO.isImm() &&
+             "printMemRegImmS10 first operand is not immedate");
       printS10ImmOperand(MI, OpNo);
       O << "(";
       printOperand(MI, OpNo+1);
@@ -198,11 +198,11 @@
     printAddr256K(const MachineInstr *MI, unsigned OpNo)
     {
       /* Note: operand 1 is an offset or symbol name. */
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         printOp(MI->getOperand(OpNo));
-        if (MI->getOperand(OpNo+1).isImmediate()) {
+        if (MI->getOperand(OpNo+1).isImm()) {
           int displ = int(MI->getOperand(OpNo+1).getImm());
           if (displ > 0)
             O << "+" << displ;
@@ -222,7 +222,7 @@
     }
 
     void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         printOp(MI->getOperand(OpNo));
@@ -231,7 +231,7 @@
     }
 
     void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         printOp(MI->getOperand(OpNo));
@@ -245,7 +245,7 @@
     }
 
     void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         int value = (int) MI->getOperand(OpNo).getImm();
         assert((value >= 0 && value < 16)
                && "Invalid negated immediate rotate 7-bit argument");
@@ -256,7 +256,7 @@
     }
 
     void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         int value = (int) MI->getOperand(OpNo).getImm();
         assert((value >= 0 && value < 32)
                && "Invalid negated immediate rotate 7-bit argument");
@@ -372,9 +372,9 @@
     default: return true;  // Unknown modifier.
     case 'L': // Write second word of DImode reference.  
       // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNo).isRegister() ||
+      if (!MI->getOperand(OpNo).isReg() ||
           OpNo+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNo+1).isRegister())
+          !MI->getOperand(OpNo+1).isReg())
         return true;
       ++OpNo;   // Return the high-part.
       break;
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
index 02490e9..cc562eb 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -60,9 +60,9 @@
   case SPU::AHIr16:
   case SPU::AIvec:
     assert(MI.getNumOperands() == 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isImmediate() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isImm() &&
            "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
     if (MI.getOperand(2).getImm() == 0) {
       sourceReg = MI.getOperand(1).getReg();
@@ -73,10 +73,10 @@
   case SPU::AIr32:
     assert(MI.getNumOperands() == 3 &&
            "wrong number of operands to AIr32");
-    if (MI.getOperand(0).isRegister() &&
-        (MI.getOperand(1).isRegister() ||
-         MI.getOperand(1).isFrameIndex()) &&
-        (MI.getOperand(2).isImmediate() &&
+    if (MI.getOperand(0).isReg() &&
+        (MI.getOperand(1).isReg() ||
+         MI.getOperand(1).isFI()) &&
+        (MI.getOperand(2).isImm() &&
          MI.getOperand(2).getImm() == 0)) {
       sourceReg = MI.getOperand(1).getReg();
       destReg = MI.getOperand(0).getReg();
@@ -103,9 +103,9 @@
   case SPU::ORf32:
   case SPU::ORf64:
     assert(MI.getNumOperands() == 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isReg() &&
            "invalid SPU OR(vec|r32|r64|gprc) instruction!");
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       sourceReg = MI.getOperand(1).getReg();
@@ -136,8 +136,8 @@
   case SPU::LQXr64:
   case SPU::LQXr32:
   case SPU::LQXr16:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
-        MI->getOperand(2).isFrameIndex()) {
+    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+        MI->getOperand(2).isFI()) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -170,8 +170,8 @@
   case SPU::STQXr32:
   case SPU::STQXr16:
     // case SPU::STQXr8:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
-        MI->getOperand(2).isFrameIndex()) {
+    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+        MI->getOperand(2).isFI()) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -273,7 +273,7 @@
   cerr << "storeRegToAddr() invoked!\n";
   abort();
 
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     /* do what storeRegToStackSlot does here */
   } else {
     unsigned Opc = 0;
@@ -297,9 +297,9 @@
       .addReg(SrcReg, false, false, isKill);
     for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
       MachineOperand &MO = Addr[i];
-      if (MO.isRegister())
+      if (MO.isReg())
         MIB.addReg(MO.getReg());
-      else if (MO.isImmediate())
+      else if (MO.isImm())
         MIB.addImm(MO.getImm());
       else
         MIB.addFrameIndex(MO.getIndex());
@@ -358,7 +358,7 @@
   cerr << "loadRegToAddr() invoked!\n";
   abort();
 
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     /* do what loadRegFromStackSlot does here... */
   } else {
     unsigned Opc = 0;
@@ -383,9 +383,9 @@
     MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
     for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
       MachineOperand &MO = Addr[i];
-      if (MO.isRegister())
+      if (MO.isReg())
         MIB.addReg(MO.getReg());
-      else if (MO.isImmediate())
+      else if (MO.isImm())
         MIB.addImm(MO.getImm());
       else
         MIB.addFrameIndex(MO.getIndex());
diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
index 882f79f..eff6d6a 100644
--- a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -328,7 +328,7 @@
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo *MFI = MF.getFrameInfo();
 
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
diff --git a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
index a2c8746..3a44b46 100644
--- a/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/llvm/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -91,7 +91,7 @@
 // pool entries aren't immediates at this stage, so we check here.
 // If it's an immediate, print it the old fashioned way. If it's
 // not, we print it as a constant pool index.
-      if(MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         O << (int64_t)MI->getOperand(OpNo).getImm();
       } else { // this is a constant pool reference: FIXME: assert this
         printOp(MI->getOperand(OpNo));
diff --git a/llvm/lib/Target/IA64/IA64Bundling.cpp b/llvm/lib/Target/IA64/IA64Bundling.cpp
index c5bc83e..ebf93b9 100644
--- a/llvm/lib/Target/IA64/IA64Bundling.cpp
+++ b/llvm/lib/Target/IA64/IA64Bundling.cpp
@@ -84,7 +84,7 @@
 
     for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
       MachineOperand &MO=CurrentInsn->getOperand(i);
-      if(MO.isRegister()) {
+      if (MO.isReg()) {
         if(MO.isUse()) { // TODO: exclude p0
           CurrentReads.insert(MO.getReg());
         }
diff --git a/llvm/lib/Target/IA64/IA64InstrInfo.cpp b/llvm/lib/Target/IA64/IA64InstrInfo.cpp
index 54bcce1..a9dce85 100644
--- a/llvm/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/llvm/lib/Target/IA64/IA64InstrInfo.cpp
@@ -31,11 +31,11 @@
   if (oc == IA64::MOV || oc == IA64::FMOV) {
   // TODO: this doesn't detect predicate moves
      assert(MI.getNumOperands() >= 2 &&
-             /* MI.getOperand(0).isRegister() &&
-             MI.getOperand(1).isRegister() && */
+             /* MI.getOperand(0).isReg() &&
+             MI.getOperand(1).isReg() && */
              "invalid register-register move instruction");
-     if( MI.getOperand(0).isRegister() &&
-         MI.getOperand(1).isRegister() ) {
+     if (MI.getOperand(0).isReg() &&
+         MI.getOperand(1).isReg()) {
        // if both operands of the MOV/FMOV are registers, then
        // yes, this is a move instruction
        sourceReg = MI.getOperand(1).getReg();
@@ -122,9 +122,9 @@
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -174,9 +174,9 @@
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
diff --git a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
index a0bc9f8..952b3f4 100644
--- a/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/llvm/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -121,7 +121,7 @@
 
   bool FP = hasFP(MF);
 
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index f384c33..85abd80 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -336,26 +336,24 @@
   // using PIC_. %call16 is used to load direct call targets
   // on PIC_ and small code size. %call_lo and %call_hi load 
   // direct call targets on PIC_ and large code size.
-  if (MI->getOpcode() == Mips::LUi && !MO.isRegister() 
-      && !MO.isImmediate()) {
+  if (MI->getOpcode() == Mips::LUi && !MO.isReg() && !MO.isImm()) {
     if ((isPIC) && (isCodeLarge))
       O << "%call_hi(";
     else
       O << "%hi(";
     closeP = true;
-  } else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isRegister() 
-             && !MO.isImmediate()) {
+  } else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isReg() && !MO.isImm()) {
     const MachineOperand &firstMO = MI->getOperand(opNum-1);
     if (firstMO.getReg() == Mips::GP)
       O << "%gp_rel(";
     else
       O << "%lo(";
     closeP = true;
-  } else if ((isPIC) && (MI->getOpcode() == Mips::LW)
-             && (!MO.isRegister()) && (!MO.isImmediate())) {
+  } else if ((isPIC) && (MI->getOpcode() == Mips::LW) &&
+             (!MO.isReg()) && (!MO.isImm())) {
     const MachineOperand &firstMO = MI->getOperand(opNum-1);
     const MachineOperand &lastMO  = MI->getOperand(opNum+1);
-    if ((firstMO.isRegister()) && (lastMO.isRegister())) {
+    if ((firstMO.isReg()) && (lastMO.isReg())) {
       if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() == Mips::GP) 
           && (!isCodeLarge))
         O << "%call16(";
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
index 4a919a0..3e6ce53 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp
@@ -24,7 +24,7 @@
     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
 
 static bool isZeroImm(const MachineOperand &op) {
-  return op.isImmediate() && op.getImm() == 0;
+  return op.isImm() && op.getImm() == 0;
 }
 
 /// Return true if the instruction is a register to register move and
@@ -60,7 +60,7 @@
 
   //  addiu $dst, $src, 0
   if (MI.getOpcode() == Mips::ADDiu) {
-    if ((MI.getOperand(1).isRegister()) && (isZeroImm(MI.getOperand(2)))) {
+    if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(1).getReg();
       return true;
@@ -79,8 +79,8 @@
 {
   if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
       (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
-    if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
-        (MI->getOperand(1).isImmediate()) &&  // the imm is zero
+    if ((MI->getOperand(2).isFI()) && // is a stack slot
+        (MI->getOperand(1).isImm()) &&  // the imm is zero
         (isZeroImm(MI->getOperand(1)))) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
@@ -100,8 +100,8 @@
 {
   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
       (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
-    if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
-        (MI->getOperand(1).isImmediate()) &&  // the imm is zero
+    if ((MI->getOperand(2).isFI()) && // is a stack slot
+        (MI->getOperand(1).isImm()) &&  // the imm is zero
         (isZeroImm(MI->getOperand(1)))) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
@@ -217,9 +217,9 @@
     .addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -267,9 +267,9 @@
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -289,10 +289,10 @@
 
   switch (MI->getOpcode()) {
   case Mips::ADDu:
-    if ((MI->getOperand(0).isRegister()) &&
-        (MI->getOperand(1).isRegister()) && 
+    if ((MI->getOperand(0).isReg()) &&
+        (MI->getOperand(1).isReg()) &&
         (MI->getOperand(1).getReg() == Mips::ZERO) &&
-        (MI->getOperand(2).isRegister())) {
+        (MI->getOperand(2).isReg())) {
       if (Ops[0] == 0) {    // COPY -> STORE
         unsigned SrcReg = MI->getOperand(2).getReg();
         bool isKill = MI->getOperand(2).isKill();
@@ -310,8 +310,8 @@
   case Mips::FMOV_SO32:
   case Mips::FMOV_AS32:
   case Mips::FMOV_D32:
-    if ((MI->getOperand(0).isRegister()) &&
-        (MI->getOperand(1).isRegister())) {
+    if ((MI->getOperand(0).isReg()) &&
+        (MI->getOperand(1).isReg())) {
       const TargetRegisterClass 
         *RC = RI.getRegClass(MI->getOperand(0).getReg());
       unsigned StoreOpc, LoadOpc;
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index de0cb52..3510141 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -348,7 +348,7 @@
   MachineFunction &MF = *MI.getParent()->getParent();
 
   unsigned i = 0;
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && 
            "Instr doesn't have FrameIndex operand!");
diff --git a/llvm/lib/Target/PIC16/PIC16AsmPrinter.cpp b/llvm/lib/Target/PIC16/PIC16AsmPrinter.cpp
index 5102e7a..d765d75 100644
--- a/llvm/lib/Target/PIC16/PIC16AsmPrinter.cpp
+++ b/llvm/lib/Target/PIC16/PIC16AsmPrinter.cpp
@@ -288,7 +288,7 @@
 void PIC16AsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) 
 {
   const MachineOperand &MO = MI->getOperand(OpNum);
-  assert(MO.isImmediate() && "Not a valid so_imm value!");
+  assert(MO.isImm() && "Not a valid so_imm value!");
   printSOImm(O, MO.getImm(), TAI);
 }
 
@@ -298,19 +298,19 @@
   const MachineOperand &MO1 = MI->getOperand(Op);
   const MachineOperand &MO2 = MI->getOperand(Op+1);
 
-  if (MO2.isFrameIndex ()) {
+  if (MO2.isFI()) {
     printOperand(MI, Op+1);
     return;
   }
 
-  if (!MO1.isRegister()) {   
+  if (!MO1.isReg()) {
     // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
 
   // If this is Stack Slot
-  if (MO1.isRegister()) {  
+  if (MO1.isReg()) {
     if (strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name, "SP") == 0) {
       O << CurrentFnName <<"_"<< MO2.getImm();
       return;
diff --git a/llvm/lib/Target/PIC16/PIC16InstrInfo.cpp b/llvm/lib/Target/PIC16/PIC16InstrInfo.cpp
index e3581ce..cc1cb88 100644
--- a/llvm/lib/Target/PIC16/PIC16InstrInfo.cpp
+++ b/llvm/lib/Target/PIC16/PIC16InstrInfo.cpp
@@ -27,7 +27,7 @@
     TM(tm), RI(*this) {}
 
 static bool isZeroImm(const MachineOperand &op) {
-  return op.isImmediate() && op.getImm() == 0;
+  return op.isImm() && op.getImm() == 0;
 }
 
 
@@ -40,8 +40,8 @@
 isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const 
 {
   if (MI->getOpcode() == PIC16::MOVF) {
-    if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
-        (MI->getOperand(1).isImmediate()) &&  // the imm is zero
+    if ((MI->getOperand(2).isFI()) && // is a stack slot
+        (MI->getOperand(1).isImm()) &&  // the imm is zero
         (isZeroImm(MI->getOperand(1)))) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
@@ -60,8 +60,8 @@
 isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const 
 {
   if (MI->getOpcode() == PIC16::MOVWF) {
-    if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
-        (MI->getOperand(1).isImmediate()) &&  // the imm is zero
+    if ((MI->getOperand(0).isFI()) && // is a stack slot
+        (MI->getOperand(1).isImm()) &&  // the imm is zero
         (isZeroImm(MI->getOperand(1)))) {
       FrameIndex = MI->getOperand(0).getIndex();
       return MI->getOperand(2).getReg();
diff --git a/llvm/lib/Target/PIC16/PIC16RegisterInfo.cpp b/llvm/lib/Target/PIC16/PIC16RegisterInfo.cpp
index 9a83155..d05f62c 100644
--- a/llvm/lib/Target/PIC16/PIC16RegisterInfo.cpp
+++ b/llvm/lib/Target/PIC16/PIC16RegisterInfo.cpp
@@ -141,7 +141,7 @@
   MachineFunction &MF = *MI.getParent()->getParent();
 
   unsigned i = 0;
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && 
            "Instr doesn't have FrameIndex operand!");
diff --git a/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index d8451bd..d164066 100644
--- a/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -123,9 +123,9 @@
 
     void printOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.isRegister()) {
+      if (MO.isReg()) {
         printRegister(MO, false);
-      } else if (MO.isImmediate()) {
+      } else if (MO.isImm()) {
         O << MO.getImm();
       } else {
         printOp(MO);
@@ -160,7 +160,7 @@
       O << (unsigned short)MI->getOperand(OpNo).getImm();
     }
     void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         O << (short)(MI->getOperand(OpNo).getImm()*4);
       } else {
         O << "lo16(";
@@ -174,7 +174,7 @@
     void printBranchOperand(const MachineInstr *MI, unsigned OpNo) {
       // Branches can take an immediate operand.  This is used by the branch
       // selection pass to print $+8, an eight byte displacement from the PC.
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         O << "$+" << MI->getOperand(OpNo).getImm()*4;
       } else {
         printOp(MI->getOperand(OpNo));
@@ -214,7 +214,7 @@
       O << "\"L" << getFunctionNumber() << "$pb\":";
     }
     void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         if (Subtarget.isDarwin()) O << "ha16(";
@@ -228,7 +228,7 @@
       }
     }
     void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         if (Subtarget.isDarwin()) O << "lo16(";
@@ -250,7 +250,7 @@
     void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
       printSymbolLo(MI, OpNo);
       O << '(';
-      if (MI->getOperand(OpNo+1).isRegister() &&
+      if (MI->getOperand(OpNo+1).isReg() &&
           MI->getOperand(OpNo+1).getReg() == PPC::R0)
         O << "0";
       else
@@ -258,12 +258,12 @@
       O << ')';
     }
     void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate())
+      if (MI->getOperand(OpNo).isImm())
         printS16X4ImmOperand(MI, OpNo);
       else
         printSymbolLo(MI, OpNo);
       O << '(';
-      if (MI->getOperand(OpNo+1).isRegister() &&
+      if (MI->getOperand(OpNo+1).isReg() &&
           MI->getOperand(OpNo+1).getReg() == PPC::R0)
         O << "0";
       else
@@ -443,16 +443,16 @@
       return false;
     case 'L': // Write second word of DImode reference.
       // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNo).isRegister() ||
+      if (!MI->getOperand(OpNo).isReg() ||
           OpNo+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNo+1).isRegister())
+          !MI->getOperand(OpNo+1).isReg())
         return true;
       ++OpNo;   // Return the high-part.
       break;
     case 'I':
       // Write 'i' if an integer constant, otherwise nothing.  Used to print
       // addi vs add, etc.
-      if (MI->getOperand(OpNo).isImmediate())
+      if (MI->getOperand(OpNo).isImm())
         O << "i";
       return false;
     }
@@ -467,7 +467,7 @@
                                           const char *ExtraCode) {
   if (ExtraCode && ExtraCode[0])
     return true; // Unknown modifier.
-  if (MI->getOperand(OpNo).isRegister())
+  if (MI->getOperand(OpNo).isReg())
     printMemRegReg(MI, OpNo);
   else
     printMemRegImm(MI, OpNo);
diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
index 2fc5b3c..add37e1 100644
--- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -103,7 +103,7 @@
       unsigned MBBStartOffset = 0;
       for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
            I != E; ++I) {
-        if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) {
+        if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
           MBBStartOffset += TII->GetInstSizeInBytes(I);
           continue;
         }
diff --git a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
index a77c726..f80442f 100644
--- a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -126,7 +126,7 @@
 
   unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
                    // or things that get fixed up later by the JIT.
-  if (MO.isRegister()) {
+  if (MO.isReg()) {
     rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
 
     // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
@@ -135,10 +135,10 @@
         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
       rv = 0x80 >> rv;
     }
-  } else if (MO.isImmediate()) {
+  } else if (MO.isImm()) {
     rv = MO.getImm();
-  } else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
-             MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
+  } else if (MO.isGlobal() || MO.isSymbol() ||
+             MO.isCPI() || MO.isJTI()) {
     unsigned Reloc = 0;
     if (MI.getOpcode() == PPC::BL_Macho || MI.getOpcode() == PPC::BL8_Macho ||
         MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF ||
@@ -193,18 +193,18 @@
     }
     
     MachineRelocation R;
-    if (MO.isGlobalAddress()) {
+    if (MO.isGlobal()) {
       R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
                                    MO.getGlobal(), 0,
                                    isa<Function>(MO.getGlobal()));
-    } else if (MO.isExternalSymbol()) {
+    } else if (MO.isSymbol()) {
       R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
                                        Reloc, MO.getSymbolName(), 0);
-    } else if (MO.isConstantPoolIndex()) {
+    } else if (MO.isCPI()) {
       R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
                                           Reloc, MO.getIndex(), 0);
     } else {
-      assert(MO.isJumpTableIndex());
+      assert(MO.isJTI());
       R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
                                           Reloc, MO.getIndex(), 0);
     }
@@ -220,7 +220,7 @@
     }
     MCE.addRelocation(R);
     
-  } else if (MO.isMachineBasicBlock()) {
+  } else if (MO.isMBB()) {
     unsigned Reloc = 0;
     unsigned Opcode = MI.getOpcode();
     if (Opcode == PPC::B || Opcode == PPC::BL_Macho ||
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 27899a7..ca65feb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -47,9 +47,9 @@
   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isReg() &&
            "invalid PPC OR instruction!");
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       sourceReg = MI.getOperand(1).getReg();
@@ -58,19 +58,19 @@
     }
   } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(2).isImmediate() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(2).isImm() &&
            "invalid PPC ADDI instruction!");
-    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
+    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
       sourceReg = MI.getOperand(1).getReg();
       destReg = MI.getOperand(0).getReg();
       return true;
     }
   } else if (oc == PPC::ORI) {             // ori r1, r2, 0
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isImmediate() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isImm() &&
            "invalid PPC ORI instruction!");
     if (MI.getOperand(2).getImm() == 0) {
       sourceReg = MI.getOperand(1).getReg();
@@ -80,16 +80,16 @@
   } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
              oc == PPC::FMRSD) {      // fmr r1, r2
     assert(MI.getNumOperands() >= 2 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
            "invalid PPC FMR instruction");
     sourceReg = MI.getOperand(1).getReg();
     destReg = MI.getOperand(0).getReg();
     return true;
   } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
     assert(MI.getNumOperands() >= 2 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
            "invalid PPC MCRF instruction");
     sourceReg = MI.getOperand(1).getReg();
     destReg = MI.getOperand(0).getReg();
@@ -106,8 +106,8 @@
   case PPC::LWZ:
   case PPC::LFS:
   case PPC::LFD:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
-        MI->getOperand(2).isFrameIndex()) {
+    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+        MI->getOperand(2).isFI()) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -124,8 +124,8 @@
   case PPC::STW:
   case PPC::STFS:
   case PPC::STFD:
-    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
-        MI->getOperand(2).isFrameIndex()) {
+    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+        MI->getOperand(2).isFI()) {
       FrameIndex = MI->getOperand(2).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -478,7 +478,7 @@
                                   SmallVectorImpl<MachineOperand> &Addr,
                                   const TargetRegisterClass *RC,
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     if (StoreRegToStackSlot(MF, SrcReg, isKill,
                             Addr[0].getIndex(), RC, NewMIs)) {
       PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
@@ -507,9 +507,9 @@
     .addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -617,7 +617,7 @@
                                    SmallVectorImpl<MachineOperand> &Addr,
                                    const TargetRegisterClass *RC,
                                    SmallVectorImpl<MachineInstr*> &NewMIs)const{
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
     return;
   }
@@ -642,9 +642,9 @@
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 014925e..586ad6b 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -629,7 +629,7 @@
 
   // Find out which operand is the frame index.
   unsigned FIOperandNo = 0;
-  while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
+  while (!MI.getOperand(FIOperandNo).isFI()) {
     ++FIOperandNo;
     assert(FIOperandNo != MI.getNumOperands() &&
            "Instr doesn't have FrameIndex operand!");
@@ -1242,7 +1242,7 @@
   if (UsesTCRet) {
     int MaxTCRetDelta = FI->getTailCallSPDelta();
     MachineOperand &StackAdjust = MBBI->getOperand(1);
-    assert( StackAdjust.isImmediate() && "Expecting immediate value.");
+    assert(StackAdjust.isImm() && "Expecting immediate value.");
     // Adjust stack pointer.
     int StackAdj = StackAdjust.getImm();
     int Delta = StackAdj - MaxTCRetDelta;
@@ -1368,7 +1368,7 @@
   } else if (RetOpcode == PPC::TCRETURNri) {
     MBBI = prior(MBB.end());
     MachineOperand &JumpTarget = MBBI->getOperand(0);
-    assert(JumpTarget.isRegister() && "Expecting register operand.");
+    assert(JumpTarget.isReg() && "Expecting register operand.");
     BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
   } else if (RetOpcode == PPC::TCRETURNai) {
     MBBI = prior(MBB.end());
@@ -1382,7 +1382,7 @@
   } else if (RetOpcode == PPC::TCRETURNri8) {
     MBBI = prior(MBB.end());
     MachineOperand &JumpTarget = MBBI->getOperand(0);
-    assert(JumpTarget.isRegister() && "Expecting register operand.");
+    assert(JumpTarget.isReg() && "Expecting register operand.");
     BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
   } else if (RetOpcode == PPC::TCRETURNai8) {
     MBBI = prior(MBB.end());
diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
index 6e8c68b..f6e3f66 100644
--- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -141,11 +141,11 @@
   const MachineOperand &MO = MI->getOperand (opNum);
   const TargetRegisterInfo &RI = *TM.getRegisterInfo();
   bool CloseParen = false;
-  if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
+  if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) {
     O << "%hi(";
     CloseParen = true;
-  } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri)
-             && !MO.isRegister() && !MO.isImmediate()) {
+  } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) &&
+             !MO.isReg() && !MO.isImm()) {
     O << "%lo(";
     CloseParen = true;
   }
@@ -190,16 +190,16 @@
     return;
   }
 
-  if (MI->getOperand(opNum+1).isRegister() &&
+  if (MI->getOperand(opNum+1).isReg() &&
       MI->getOperand(opNum+1).getReg() == SP::G0)
     return;   // don't print "+%g0"
-  if (MI->getOperand(opNum+1).isImmediate() &&
+  if (MI->getOperand(opNum+1).isImm() &&
       MI->getOperand(opNum+1).getImm() == 0)
     return;   // don't print "+0"
 
   O << "+";
-  if (MI->getOperand(opNum+1).isGlobalAddress() ||
-      MI->getOperand(opNum+1).isConstantPoolIndex()) {
+  if (MI->getOperand(opNum+1).isGlobal() ||
+      MI->getOperand(opNum+1).isCPI()) {
     O << "%lo(";
     printOperand(MI, opNum+1);
     O << ")";
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 927d268..0d7370b 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -25,7 +25,7 @@
 }
 
 static bool isZeroImm(const MachineOperand &op) {
-  return op.isImmediate() && op.getImm() == 0;
+  return op.isImm() && op.getImm() == 0;
 }
 
 /// Return true if the instruction is a register to register move and
@@ -48,7 +48,7 @@
       return true;
     }
   } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
-             isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
+             isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
     DstReg = MI.getOperand(0).getReg();
     SrcReg = MI.getOperand(1).getReg();
     return true;
@@ -71,7 +71,7 @@
   if (MI->getOpcode() == SP::LDri ||
       MI->getOpcode() == SP::LDFri ||
       MI->getOpcode() == SP::LDDFri) {
-    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
+    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
         MI->getOperand(2).getImm() == 0) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
@@ -90,7 +90,7 @@
   if (MI->getOpcode() == SP::STri ||
       MI->getOpcode() == SP::STFri ||
       MI->getOpcode() == SP::STDFri) {
-    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
+    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
         MI->getOperand(1).getImm() == 0) {
       FrameIndex = MI->getOperand(0).getIndex();
       return MI->getOperand(2).getReg();
@@ -168,12 +168,12 @@
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else {
-      assert(MO.isFrameIndex());
+      assert(MO.isFI());
       MIB.addFrameIndex(MO.getIndex());
     }
   }
@@ -212,12 +212,12 @@
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else {
-      assert(MO.isFrameIndex());
+      assert(MO.isFI());
       MIB.addFrameIndex(MO.getIndex());
     }
   }
@@ -236,8 +236,8 @@
   MachineInstr *NewMI = NULL;
   switch (MI->getOpcode()) {
   case SP::ORrr:
-    if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
-        MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
+    if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
+        MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
       if (OpNum == 0)    // COPY -> STORE
         NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
                                    .addReg(MI->getOperand(2).getReg());
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
index 92e92ea..94853a6 100644
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -80,7 +80,7 @@
 
   unsigned i = 0;
   MachineInstr &MI = *II;
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
diff --git a/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index 9415871..e66edca 100644
--- a/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/llvm/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -546,9 +546,9 @@
   const MachineOperand &DispSpec = MI->getOperand(Op+3);
 
   bool NotRIPRel = IndexReg.getReg() || BaseReg.getReg();
-  if (DispSpec.isGlobalAddress() ||
-      DispSpec.isConstantPoolIndex() ||
-      DispSpec.isJumpTableIndex()) {
+  if (DispSpec.isGlobal() ||
+      DispSpec.isCPI() ||
+      DispSpec.isJTI()) {
     printOperand(MI, Op+3, "mem", NotRIPRel);
   } else {
     int DispVal = DispSpec.getImm();
@@ -675,7 +675,7 @@
     case 'w': // Print HImode register
     case 'k': // Print SImode register
     case 'q': // Print DImode register
-      if (MI->getOperand(OpNo).isRegister())
+      if (MI->getOperand(OpNo).isReg())
         return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
       printOperand(MI, OpNo);
       return false;
diff --git a/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
index fdec3bc..a9141d3 100644
--- a/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
+++ b/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
@@ -298,8 +298,8 @@
     NeedPlus = true;
   }
 
-  if (DispSpec.isGlobalAddress() || DispSpec.isConstantPoolIndex() ||
-      DispSpec.isJumpTableIndex()) {
+  if (DispSpec.isGlobal() || DispSpec.isCPI() ||
+      DispSpec.isJTI()) {
     if (NeedPlus)
       O << " + ";
     printOp(DispSpec, "mem");
diff --git a/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h b/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
index ff31617..9762e93 100644
--- a/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
+++ b/llvm/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
@@ -44,7 +44,7 @@
   void printOperand(const MachineInstr *MI, unsigned OpNo,
                     const char *Modifier = 0) {
     const MachineOperand &MO = MI->getOperand(OpNo);
-    if (MO.isRegister()) {
+    if (MO.isReg()) {
       assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
              "Not physreg??");
       O << TM.getRegisterInfo()->get(MO.getReg()).Name;  // Capitalized names
diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index 1c81b4b..37c1e99 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -268,7 +268,7 @@
   
   // Otherwise, this is something that requires a relocation.  Emit it as such
   // now.
-  if (RelocOp->isGlobalAddress()) {
+  if (RelocOp->isGlobal()) {
     // In 64-bit static small code model, we could potentially emit absolute.
     // But it's probably not beneficial.
     //  89 05 00 00 00 00     mov    %eax,0(%rip)  # PC-relative
@@ -279,11 +279,11 @@
     bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
     emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
                       PCAdj, NeedStub, isLazy);
-  } else if (RelocOp->isConstantPoolIndex()) {
+  } else if (RelocOp->isCPI()) {
     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
     emitConstPoolAddress(RelocOp->getIndex(), rt,
                          RelocOp->getOffset(), PCAdj);
-  } else if (RelocOp->isJumpTableIndex()) {
+  } else if (RelocOp->isJTI()) {
     unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
     emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
   } else {
@@ -299,16 +299,16 @@
   const MachineOperand *DispForReloc = 0;
   
   // Figure out what sort of displacement we have to handle here.
-  if (Op3.isGlobalAddress()) {
+  if (Op3.isGlobal()) {
     DispForReloc = &Op3;
-  } else if (Op3.isConstantPoolIndex()) {
+  } else if (Op3.isCPI()) {
     if (Is64BitMode || IsPIC) {
       DispForReloc = &Op3;
     } else {
       DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
       DispVal += Op3.getOffset();
     }
-  } else if (Op3.isJumpTableIndex()) {
+  } else if (Op3.isJTI()) {
     if (Is64BitMode || IsPIC) {
       DispForReloc = &Op3;
     } else {
@@ -522,14 +522,14 @@
       const MachineOperand &MO = MI.getOperand(CurOp++);
 
       DOUT << "RawFrm CurOp " << CurOp << "\n";
-      DOUT << "isMachineBasicBlock " << MO.isMachineBasicBlock() << "\n";
-      DOUT << "isGlobalAddress " << MO.isGlobalAddress() << "\n";
-      DOUT << "isExternalSymbol " << MO.isExternalSymbol() << "\n";
-      DOUT << "isImmediate " << MO.isImmediate() << "\n";
+      DOUT << "isMBB " << MO.isMBB() << "\n";
+      DOUT << "isGlobal " << MO.isGlobal() << "\n";
+      DOUT << "isSymbol " << MO.isSymbol() << "\n";
+      DOUT << "isImm " << MO.isImm() << "\n";
 
-      if (MO.isMachineBasicBlock()) {
+      if (MO.isMBB()) {
         emitPCRelativeBlockAddress(MO.getMBB());
-      } else if (MO.isGlobalAddress()) {
+      } else if (MO.isGlobal()) {
         // Assume undefined functions may be outside the Small codespace.
         bool NeedStub = 
           (Is64BitMode && 
@@ -538,9 +538,9 @@
           Opcode == X86::TAILJMPd;
         emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
                           0, 0, NeedStub);
-      } else if (MO.isExternalSymbol()) {
+      } else if (MO.isSymbol()) {
         emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
-      } else if (MO.isImmediate()) {
+      } else if (MO.isImm()) {
         emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
       } else {
         assert(0 && "Unknown RawFrm operand!");
@@ -554,7 +554,7 @@
     if (CurOp != NumOps) {
       const MachineOperand &MO1 = MI.getOperand(CurOp++);
       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
-      if (MO1.isImmediate())
+      if (MO1.isImm())
         emitConstant(MO1.getImm(), Size);
       else {
         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
@@ -562,16 +562,16 @@
         // This should not occur on Darwin for relocatable objects.
         if (Opcode == X86::MOV64ri)
           rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
-        if (MO1.isGlobalAddress()) {
+        if (MO1.isGlobal()) {
           bool NeedStub = isa<Function>(MO1.getGlobal());
           bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
                             NeedStub, isLazy);
-        } else if (MO1.isExternalSymbol())
+        } else if (MO1.isSymbol())
           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
-        else if (MO1.isConstantPoolIndex())
+        else if (MO1.isCPI())
           emitConstPoolAddress(MO1.getIndex(), rt);
-        else if (MO1.isJumpTableIndex())
+        else if (MO1.isJTI())
           emitJumpTableAddress(MO1.getIndex(), rt);
       }
     }
@@ -627,23 +627,23 @@
     if (CurOp != NumOps) {
       const MachineOperand &MO1 = MI.getOperand(CurOp++);
       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
-      if (MO1.isImmediate())
+      if (MO1.isImm())
         emitConstant(MO1.getImm(), Size);
       else {
         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
         if (Opcode == X86::MOV64ri32)
           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
-        if (MO1.isGlobalAddress()) {
+        if (MO1.isGlobal()) {
           bool NeedStub = isa<Function>(MO1.getGlobal());
           bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
           emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
                             NeedStub, isLazy);
-        } else if (MO1.isExternalSymbol())
+        } else if (MO1.isSymbol())
           emitExternalSymbolAddress(MO1.getSymbolName(), rt);
-        else if (MO1.isConstantPoolIndex())
+        else if (MO1.isCPI())
           emitConstPoolAddress(MO1.getIndex(), rt);
-        else if (MO1.isJumpTableIndex())
+        else if (MO1.isJTI())
           emitJumpTableAddress(MO1.getIndex(), rt);
       }
     }
@@ -654,7 +654,7 @@
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m: {
     intptr_t PCAdj = (CurOp+4 != NumOps) ?
-      (MI.getOperand(CurOp+4).isImmediate() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
+      (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
 
     MCE.emitByte(BaseOpcode);
     emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
@@ -664,23 +664,23 @@
     if (CurOp != NumOps) {
       const MachineOperand &MO = MI.getOperand(CurOp++);
       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
-      if (MO.isImmediate())
+      if (MO.isImm())
         emitConstant(MO.getImm(), Size);
       else {
         unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
           : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
         if (Opcode == X86::MOV64mi32)
           rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
-        if (MO.isGlobalAddress()) {
+        if (MO.isGlobal()) {
           bool NeedStub = isa<Function>(MO.getGlobal());
           bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
           emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
                             NeedStub, isLazy);
-        } else if (MO.isExternalSymbol())
+        } else if (MO.isSymbol())
           emitExternalSymbolAddress(MO.getSymbolName(), rt);
-        else if (MO.isConstantPoolIndex())
+        else if (MO.isCPI())
           emitConstPoolAddress(MO.getIndex(), rt);
-        else if (MO.isJumpTableIndex())
+        else if (MO.isJTI())
           emitJumpTableAddress(MO.getIndex(), rt);
       }
     }
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index ccb344d..3908228 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -168,7 +168,7 @@
 /// getFPReg - Return the X86::FPx register number for the specified operand.
 /// For example, this returns 3 for X86::FP3.
 static unsigned getFPReg(const MachineOperand &MO) {
-  assert(MO.isRegister() && "Expected an FP register!");
+  assert(MO.isReg() && "Expected an FP register!");
   unsigned Reg = MO.getReg();
   assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
   return Reg - X86::FP0;
@@ -240,7 +240,7 @@
     SmallVector<unsigned, 8> DeadRegs;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       const MachineOperand &MO = MI->getOperand(i);
-      if (MO.isRegister() && MO.isDead())
+      if (MO.isReg() && MO.isDead())
         DeadRegs.push_back(MO.getReg());
     }
 
@@ -1021,7 +1021,7 @@
     unsigned NumKills = 0;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &Op = MI->getOperand(i);
-      if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
+      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
         continue;
       assert(Op.isUse() && "Only handle inline asm uses right now");
       
@@ -1061,7 +1061,7 @@
     
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &Op = MI->getOperand(i);
-      if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
+      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
         continue;
       // FP Register uses must be kills unless there are two uses of the same
       // register, in which case only one will be a kill.
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index a60b13e..658d939 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -703,10 +703,10 @@
     bool ContainsFPCode = false;
     for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
          !ContainsFPCode && I != E; ++I) {
-      if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
+      if (I->getNumOperands() != 0 && I->getOperand(0).isReg()) {
         const TargetRegisterClass *clas;
         for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
-          if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
+          if (I->getOperand(op).isReg() && I->getOperand(op).isDef() &&
             TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
               ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == 
                  X86::RFP32RegisterClass ||
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f65167b..7f84d4c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -6385,10 +6385,10 @@
     tt = t1;
 
   unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
-  assert((argOpers[valArgIndx]->isRegister() ||
-          argOpers[valArgIndx]->isImmediate()) &&
+  assert((argOpers[valArgIndx]->isReg() ||
+          argOpers[valArgIndx]->isImm()) &&
          "invalid operand");
-  if (argOpers[valArgIndx]->isRegister())
+  if (argOpers[valArgIndx]->isReg())
     MIB = BuildMI(newMBB, TII->get(regOpc), t2);
   else
     MIB = BuildMI(newMBB, TII->get(immOpc), t2);
@@ -6507,19 +6507,19 @@
     tt2 = t2;
   }
 
-  assert((argOpers[4]->isRegister() || argOpers[4]->isImmediate()) &&
+  assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
          "invalid operand");
   unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
   unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
-  if (argOpers[4]->isRegister())
+  if (argOpers[4]->isReg())
     MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
   else
     MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
   MIB.addReg(tt1);
   (*MIB).addOperand(*argOpers[4]);
-  assert(argOpers[5]->isRegister() == argOpers[4]->isRegister());
-  assert(argOpers[5]->isImmediate() == argOpers[4]->isImmediate());
-  if (argOpers[5]->isRegister())
+  assert(argOpers[5]->isReg() == argOpers[4]->isReg());
+  assert(argOpers[5]->isImm() == argOpers[4]->isImm());
+  if (argOpers[5]->isReg())
     MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
   else
     MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
@@ -6613,12 +6613,12 @@
     (*MIB).addOperand(*argOpers[i]);
 
   // We only support register and immediate values
-  assert((argOpers[valArgIndx]->isRegister() ||
-          argOpers[valArgIndx]->isImmediate()) &&
+  assert((argOpers[valArgIndx]->isReg() ||
+          argOpers[valArgIndx]->isImm()) &&
          "invalid operand");
   
   unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);  
-  if (argOpers[valArgIndx]->isRegister())
+  if (argOpers[valArgIndx]->isReg())
     MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
   else 
     MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
@@ -6766,7 +6766,7 @@
 
     X86AddressMode AM;
     MachineOperand &Op = MI->getOperand(0);
-    if (Op.isRegister()) {
+    if (Op.isReg()) {
       AM.BaseType = X86AddressMode::RegBase;
       AM.Base.Reg = Op.getReg();
     } else {
@@ -6774,13 +6774,13 @@
       AM.Base.FrameIndex = Op.getIndex();
     }
     Op = MI->getOperand(1);
-    if (Op.isImmediate())
+    if (Op.isImm())
       AM.Scale = Op.getImm();
     Op = MI->getOperand(2);
-    if (Op.isImmediate())
+    if (Op.isImm())
       AM.IndexReg = Op.getImm();
     Op = MI->getOperand(3);
-    if (Op.isGlobalAddress()) {
+    if (Op.isGlobal()) {
       AM.GV = Op.getGlobal();
     } else {
       AM.Disp = Op.getImm();
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index cac35b1..6a1d166 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -679,8 +679,8 @@
   case X86::MMX_MOVD64rr:
   case X86::MMX_MOVQ64rr:
     assert(MI.getNumOperands() >= 2 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
            "invalid register-register move instruction");
     sourceReg = MI.getOperand(1).getReg();
     destReg = MI.getOperand(0).getReg();
@@ -705,8 +705,8 @@
   case X86::MOVAPDrm:
   case X86::MMX_MOVD64rm:
   case X86::MMX_MOVQ64rm:
-    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
-        MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
+    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
+        MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
         MI->getOperand(2).getImm() == 1 &&
         MI->getOperand(3).getReg() == 0 &&
         MI->getOperand(4).getImm() == 0) {
@@ -736,8 +736,8 @@
   case X86::MMX_MOVD64mr:
   case X86::MMX_MOVQ64mr:
   case X86::MMX_MOVNTQmr:
-    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
-        MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
+    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
+        MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
         MI->getOperand(1).getImm() == 1 &&
         MI->getOperand(2).getReg() == 0 &&
         MI->getOperand(3).getImm() == 0) {
@@ -789,17 +789,17 @@
     case X86::MMX_MOVD64rm:
     case X86::MMX_MOVQ64rm: {
       // Loads from constant pools are trivially rematerializable.
-      if (MI->getOperand(1).isRegister() &&
-          MI->getOperand(2).isImmediate() &&
-          MI->getOperand(3).isRegister() && MI->getOperand(3).getReg() == 0 &&
-          (MI->getOperand(4).isConstantPoolIndex() ||
-           (MI->getOperand(4).isGlobalAddress() &&
+      if (MI->getOperand(1).isReg() &&
+          MI->getOperand(2).isImm() &&
+          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
+          (MI->getOperand(4).isCPI() ||
+           (MI->getOperand(4).isGlobal() &&
             isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
         unsigned BaseReg = MI->getOperand(1).getReg();
         if (BaseReg == 0)
           return true;
         // Allow re-materialization of PIC load.
-        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobalAddress())
+        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
           return false;
         const MachineFunction &MF = *MI->getParent()->getParent();
         const MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -819,11 +819,11 @@
  
      case X86::LEA32r:
      case X86::LEA64r: {
-       if (MI->getOperand(2).isImmediate() &&
-           MI->getOperand(3).isRegister() && MI->getOperand(3).getReg() == 0 &&
-           !MI->getOperand(4).isRegister()) {
+       if (MI->getOperand(2).isImm() &&
+           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
+           !MI->getOperand(4).isReg()) {
          // lea fi#, lea GV, etc. are all rematerializable.
-         if (!MI->getOperand(1).isRegister())
+         if (!MI->getOperand(1).isReg())
            return true;
          unsigned BaseReg = MI->getOperand(1).getReg();
          if (BaseReg == 0)
@@ -857,7 +857,7 @@
     bool SeenDef = false;
     for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
       MachineOperand &MO = I->getOperand(j);
-      if (!MO.isRegister())
+      if (!MO.isReg())
         continue;
       if (MO.getReg() == X86::EFLAGS) {
         if (MO.isUse())
@@ -880,7 +880,7 @@
                                  MachineBasicBlock::iterator I,
                                  unsigned DestReg,
                                  const MachineInstr *Orig) const {
-  unsigned SubIdx = Orig->getOperand(0).isRegister()
+  unsigned SubIdx = Orig->getOperand(0).isReg()
     ? Orig->getOperand(0).getSubReg() : 0;
   bool ChangeSubIdx = SubIdx != 0;
   if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
@@ -942,14 +942,14 @@
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     // Loads from constant pools are trivially invariant.
-    if (MO.isConstantPoolIndex())
+    if (MO.isCPI())
       return true;
 
-    if (MO.isGlobalAddress())
+    if (MO.isGlobal())
       return isGVStub(MO.getGlobal(), TM);
 
     // If this is a load from an invariant stack slot, the load is a constant.
-    if (MO.isFrameIndex()) {
+    if (MO.isFI()) {
       const MachineFrameInfo &MFI =
         *MI->getParent()->getParent()->getFrameInfo();
       int Idx = MO.getIndex();
@@ -967,7 +967,7 @@
 static bool hasLiveCondCodeDef(MachineInstr *MI) {
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
-    if (MO.isRegister() && MO.isDef() &&
+    if (MO.isReg() && MO.isDef() &&
         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
       return true;
     }
@@ -1162,7 +1162,7 @@
     case X86::ADD64ri32:
     case X86::ADD64ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
-      if (MI->getOperand(2).isImmediate())
+      if (MI->getOperand(2).isImm())
         NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
                              .addReg(Dest, true, false, false, isDead),
                              Src, isKill, MI->getOperand(2).getImm());
@@ -1170,7 +1170,7 @@
     case X86::ADD32ri:
     case X86::ADD32ri8:
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
-      if (MI->getOperand(2).isImmediate()) {
+      if (MI->getOperand(2).isImm()) {
         unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
         NewMI = addRegOffset(BuildMI(MF, get(Opc))
                              .addReg(Dest, true, false, false, isDead),
@@ -1181,7 +1181,7 @@
     case X86::ADD16ri8:
       if (DisableLEA16) return 0;
       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
-      if (MI->getOperand(2).isImmediate())
+      if (MI->getOperand(2).isImm())
         NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
                              .addReg(Dest, true, false, false, isDead),
                              Src, isKill, MI->getOperand(2).getImm());
@@ -1190,7 +1190,7 @@
       if (DisableLEA16) return 0;
     case X86::SHL32ri:
     case X86::SHL64ri: {
-      assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
+      assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
              "Unknown shl instruction!");
       unsigned ShAmt = MI->getOperand(2).getImm();
       if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
@@ -1544,20 +1544,20 @@
 
 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
                                                      MachineOperand &MO) {
-  if (MO.isRegister())
+  if (MO.isReg())
     MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
                      MO.isKill(), MO.isDead(), MO.getSubReg());
-  else if (MO.isImmediate())
+  else if (MO.isImm())
     MIB = MIB.addImm(MO.getImm());
-  else if (MO.isFrameIndex())
+  else if (MO.isFI())
     MIB = MIB.addFrameIndex(MO.getIndex());
-  else if (MO.isGlobalAddress())
+  else if (MO.isGlobal())
     MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
-  else if (MO.isConstantPoolIndex())
+  else if (MO.isCPI())
     MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
-  else if (MO.isJumpTableIndex())
+  else if (MO.isJTI())
     MIB = MIB.addJumpTableIndex(MO.getIndex());
-  else if (MO.isExternalSymbol())
+  else if (MO.isSymbol())
     MIB = MIB.addExternalSymbol(MO.getSymbolName());
   else
     assert(0 && "Unknown operand for X86InstrAddOperand!");
@@ -1916,7 +1916,7 @@
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (i == OpNo) {
-      assert(MO.isRegister() && "Expected to fold into reg operand!");
+      assert(MO.isReg() && "Expected to fold into reg operand!");
       unsigned NumAddrOps = MOs.size();
       for (unsigned i = 0; i != NumAddrOps; ++i)
         MIB = X86InstrAddOperand(MIB, MOs[i]);
@@ -1958,8 +1958,8 @@
   // instruction is different than folding it other places.  It requires
   // replacing the *two* registers with the memory location.
   if (isTwoAddr && NumOps >= 2 && i < 2 &&
-      MI->getOperand(0).isRegister() && 
-      MI->getOperand(1).isRegister() &&
+      MI->getOperand(0).isReg() &&
+      MI->getOperand(1).isReg() &&
       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 
     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
     isTwoAddrFold = true;
@@ -2190,7 +2190,7 @@
     MachineOperand &Op = MI->getOperand(i);
     if (i >= Index && i < Index+4)
       AddrOps.push_back(Op);
-    else if (Op.isRegister() && Op.isImplicit())
+    else if (Op.isReg() && Op.isImplicit())
       ImpOps.push_back(Op);
     else if (i < Index)
       BeforeOps.push_back(Op);
@@ -2205,7 +2205,7 @@
       // Address operands cannot be marked isKill.
       for (unsigned i = 1; i != 5; ++i) {
         MachineOperand &MO = NewMIs[0]->getOperand(i);
-        if (MO.isRegister())
+        if (MO.isReg())
           MO.setIsKill(false);
       }
     }
@@ -2411,7 +2411,7 @@
 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
 /// e.g. r8, xmm8, etc.
 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
-  if (!MO.isRegister()) return false;
+  if (!MO.isReg()) return false;
   switch (MO.getReg()) {
   default: break;
   case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
@@ -2452,7 +2452,7 @@
     unsigned i = isTwoAddr ? 1 : 0;
     for (unsigned e = NumOps; i != e; ++i) {
       const MachineOperand& MO = MI.getOperand(i);
-      if (MO.isRegister()) {
+      if (MO.isReg()) {
         unsigned Reg = MO.getReg();
         if (isX86_64NonExtLowByteReg(Reg))
           REX |= 0x40;
@@ -2482,7 +2482,7 @@
       i = isTwoAddr ? 2 : 1;
       for (; i != NumOps; ++i) {
         const MachineOperand& MO = MI.getOperand(i);
-        if (MO.isRegister()) {
+        if (MO.isReg()) {
           if (isX86_64ExtendedReg(MO))
             REX |= 1 << Bit;
           Bit++;
@@ -2502,7 +2502,7 @@
       unsigned Bit = 0;
       for (; i != e; ++i) {
         const MachineOperand& MO = MI.getOperand(i);
-        if (MO.isRegister()) {
+        if (MO.isReg()) {
           if (isX86_64ExtendedReg(MO))
             REX |= 1 << Bit;
           Bit++;
@@ -2581,11 +2581,11 @@
   }
   
   // Otherwise, this is something that requires a relocation.
-  if (RelocOp->isGlobalAddress()) {
+  if (RelocOp->isGlobal()) {
     FinalSize += sizeGlobalAddress(false);
-  } else if (RelocOp->isConstantPoolIndex()) {
+  } else if (RelocOp->isCPI()) {
     FinalSize += sizeConstPoolAddress(false);
-  } else if (RelocOp->isJumpTableIndex()) {
+  } else if (RelocOp->isJTI()) {
     FinalSize += sizeJumpTableAddress(false);
   } else {
     assert(0 && "Unknown value to relocate!");
@@ -2601,15 +2601,15 @@
   unsigned FinalSize = 0;
   
   // Figure out what sort of displacement we have to handle here.
-  if (Op3.isGlobalAddress()) {
+  if (Op3.isGlobal()) {
     DispForReloc = &Op3;
-  } else if (Op3.isConstantPoolIndex()) {
+  } else if (Op3.isCPI()) {
     if (Is64BitMode || IsPIC) {
       DispForReloc = &Op3;
     } else {
       DispVal = 1;
     }
-  } else if (Op3.isJumpTableIndex()) {
+  } else if (Op3.isJTI()) {
     if (Is64BitMode || IsPIC) {
       DispForReloc = &Op3;
     } else {
@@ -2774,13 +2774,13 @@
 
     if (CurOp != NumOps) {
       const MachineOperand &MO = MI.getOperand(CurOp++);
-      if (MO.isMachineBasicBlock()) {
+      if (MO.isMBB()) {
         FinalSize += sizePCRelativeBlockAddress();
-      } else if (MO.isGlobalAddress()) {
+      } else if (MO.isGlobal()) {
         FinalSize += sizeGlobalAddress(false);
-      } else if (MO.isExternalSymbol()) {
+      } else if (MO.isSymbol()) {
         FinalSize += sizeExternalSymbolAddress(false);
-      } else if (MO.isImmediate()) {
+      } else if (MO.isImm()) {
         FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
       } else {
         assert(0 && "Unknown RawFrm operand!");
@@ -2795,19 +2795,19 @@
     if (CurOp != NumOps) {
       const MachineOperand &MO1 = MI.getOperand(CurOp++);
       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
-      if (MO1.isImmediate())
+      if (MO1.isImm())
         FinalSize += sizeConstant(Size);
       else {
         bool dword = false;
         if (Opcode == X86::MOV64ri)
           dword = true; 
-        if (MO1.isGlobalAddress()) {
+        if (MO1.isGlobal()) {
           FinalSize += sizeGlobalAddress(dword);
-        } else if (MO1.isExternalSymbol())
+        } else if (MO1.isSymbol())
           FinalSize += sizeExternalSymbolAddress(dword);
-        else if (MO1.isConstantPoolIndex())
+        else if (MO1.isCPI())
           FinalSize += sizeConstPoolAddress(dword);
-        else if (MO1.isJumpTableIndex())
+        else if (MO1.isJTI())
           FinalSize += sizeJumpTableAddress(dword);
       }
     }
@@ -2867,19 +2867,19 @@
     if (CurOp != NumOps) {
       const MachineOperand &MO1 = MI.getOperand(CurOp++);
       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
-      if (MO1.isImmediate())
+      if (MO1.isImm())
         FinalSize += sizeConstant(Size);
       else {
         bool dword = false;
         if (Opcode == X86::MOV64ri32)
           dword = true;
-        if (MO1.isGlobalAddress()) {
+        if (MO1.isGlobal()) {
           FinalSize += sizeGlobalAddress(dword);
-        } else if (MO1.isExternalSymbol())
+        } else if (MO1.isSymbol())
           FinalSize += sizeExternalSymbolAddress(dword);
-        else if (MO1.isConstantPoolIndex())
+        else if (MO1.isCPI())
           FinalSize += sizeConstPoolAddress(dword);
-        else if (MO1.isJumpTableIndex())
+        else if (MO1.isJTI())
           FinalSize += sizeJumpTableAddress(dword);
       }
     }
@@ -2897,19 +2897,19 @@
     if (CurOp != NumOps) {
       const MachineOperand &MO = MI.getOperand(CurOp++);
       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
-      if (MO.isImmediate())
+      if (MO.isImm())
         FinalSize += sizeConstant(Size);
       else {
         bool dword = false;
         if (Opcode == X86::MOV64mi32)
           dword = true;
-        if (MO.isGlobalAddress()) {
+        if (MO.isGlobal()) {
           FinalSize += sizeGlobalAddress(dword);
-        } else if (MO.isExternalSymbol())
+        } else if (MO.isSymbol())
           FinalSize += sizeExternalSymbolAddress(dword);
-        else if (MO.isConstantPoolIndex())
+        else if (MO.isCPI())
           FinalSize += sizeConstPoolAddress(dword);
-        else if (MO.isJumpTableIndex())
+        else if (MO.isJTI())
           FinalSize += sizeJumpTableAddress(dword);
       }
     }
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 20f0010..b2de310 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -228,20 +228,20 @@
 }
 
 inline static bool isScale(const MachineOperand &MO) {
-  return MO.isImmediate() &&
+  return MO.isImm() &&
     (MO.getImm() == 1 || MO.getImm() == 2 ||
      MO.getImm() == 4 || MO.getImm() == 8);
 }
 
 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
-  if (MI->getOperand(Op).isFrameIndex()) return true;
+  if (MI->getOperand(Op).isFI()) return true;
   return Op+4 <= MI->getNumOperands() &&
-    MI->getOperand(Op  ).isRegister() && isScale(MI->getOperand(Op+1)) &&
-    MI->getOperand(Op+2).isRegister() &&
-    (MI->getOperand(Op+3).isImmediate() ||
-     MI->getOperand(Op+3).isGlobalAddress() ||
-     MI->getOperand(Op+3).isConstantPoolIndex() ||
-     MI->getOperand(Op+3).isJumpTableIndex());
+    MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
+    MI->getOperand(Op+2).isReg() &&
+    (MI->getOperand(Op+3).isImm() ||
+     MI->getOperand(Op+3).isGlobal() ||
+     MI->getOperand(Op+3).isCPI() ||
+     MI->getOperand(Op+3).isJTI());
 }
 
 class X86InstrInfo : public TargetInstrInfoImpl {
diff --git a/llvm/lib/Target/X86/X86MachineFunctionInfo.h b/llvm/lib/Target/X86/X86MachineFunctionInfo.h
index edce2a9..df79520 100644
--- a/llvm/lib/Target/X86/X86MachineFunctionInfo.h
+++ b/llvm/lib/Target/X86/X86MachineFunctionInfo.h
@@ -58,8 +58,9 @@
   /// holds the virtual register into which the sret argument is passed.
   unsigned SRetReturnReg;
 
-  /// GlobalBaseReg - keeps track of the virtual register mapped onto global
-  /// base register.
+  /// GlobalBaseReg - keeps track of the virtual register initialized for
+  /// use as the global base register. This is used for PIC in some PIC
+  /// relocation models.
   unsigned GlobalBaseReg;
 
 public:
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 5b6fc07..97e1de7 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -416,7 +416,7 @@
   unsigned i = 0;
   MachineInstr &MI = *II;
   MachineFunction &MF = *MI.getParent()->getParent();
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
@@ -895,7 +895,7 @@
   if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
     MBBI = prior(MBB.end());
     MachineOperand &DestAddr  = MBBI->getOperand(0);
-    assert(DestAddr.isRegister() && "Offset should be in register!");
+    assert(DestAddr.isReg() && "Offset should be in register!");
     BuildMI(MBB, MBBI,
             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
             StackPtr).addReg(DestAddr.getReg());
@@ -905,7 +905,7 @@
     MBBI = prior(MBB.end());
     MachineOperand &JumpTarget = MBBI->getOperand(0);
     MachineOperand &StackAdjust = MBBI->getOperand(1);
-    assert( StackAdjust.isImmediate() && "Expecting immediate value.");
+    assert(StackAdjust.isImm() && "Expecting immediate value.");
 
     // Adjust stack pointer.
     int StackAdj = StackAdjust.getImm();