[WebAssembly] Add except_ref as a first-class type
Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]].
Reviewers: dschuff
Subscribers: jfb, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D43706
llvm-svn: 326985
diff --git a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
index 73d9b3d..639dd63 100644
--- a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
+++ b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp
@@ -220,6 +220,7 @@
case WebAssembly::ExprType::B8x16: O << "b8x16"; break;
case WebAssembly::ExprType::B16x8: O << "b16x8"; break;
case WebAssembly::ExprType::B32x4: O << "b32x4"; break;
+ case WebAssembly::ExprType::ExceptRef: O << "except_ref"; break;
}
}
@@ -238,6 +239,8 @@
case MVT::v4i32:
case MVT::v4f32:
return "v128";
+ case MVT::ExceptRef:
+ return "except_ref";
default:
llvm_unreachable("unsupported type");
}
@@ -253,6 +256,8 @@
return "f32";
case wasm::ValType::F64:
return "f64";
+ case wasm::ValType::EXCEPT_REF:
+ return "except_ref";
}
llvm_unreachable("unsupported type");
}
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
index e7c8809..a51fb92 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
@@ -135,6 +135,7 @@
case MVT::i64: return wasm::ValType::I64;
case MVT::f32: return wasm::ValType::F32;
case MVT::f64: return wasm::ValType::F64;
+ case MVT::ExceptRef: return wasm::ValType::EXCEPT_REF;
default: llvm_unreachable("unexpected type");
}
}
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
index e27a740..364aac3 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
@@ -159,18 +159,19 @@
/// This is used to indicate block signatures.
enum class ExprType : unsigned {
- Void = 0x40,
- I32 = 0x7F,
- I64 = 0x7E,
- F32 = 0x7D,
- F64 = 0x7C,
- I8x16 = 0x7B,
- I16x8 = 0x7A,
- I32x4 = 0x79,
- F32x4 = 0x78,
- B8x16 = 0x77,
- B16x8 = 0x76,
- B32x4 = 0x75
+ Void = 0x40,
+ I32 = 0x7F,
+ I64 = 0x7E,
+ F32 = 0x7D,
+ F64 = 0x7C,
+ I8x16 = 0x7B,
+ I16x8 = 0x7A,
+ I32x4 = 0x79,
+ F32x4 = 0x78,
+ B8x16 = 0x77,
+ B16x8 = 0x76,
+ B32x4 = 0x75,
+ ExceptRef = 0x68
};
/// Instruction opcodes emitted via means other than CodeGen.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
index 21e0f6b..cab2100 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
@@ -249,6 +249,7 @@
case MVT::v8i16: retType = WebAssembly::ExprType::I16x8; break;
case MVT::v4i32: retType = WebAssembly::ExprType::I32x4; break;
case MVT::v4f32: retType = WebAssembly::ExprType::F32x4; break;
+ case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;
default: llvm_unreachable("unexpected return type");
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
index e2edb92..e6229b9 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
@@ -86,6 +86,8 @@
return WebAssembly::DROP_F64;
if (RC == &WebAssembly::V128RegClass)
return WebAssembly::DROP_V128;
+ if (RC == &WebAssembly::EXCEPT_REFRegClass)
+ return WebAssembly::DROP_EXCEPT_REF;
llvm_unreachable("Unexpected register class");
}
@@ -101,6 +103,8 @@
return WebAssembly::GET_LOCAL_F64;
if (RC == &WebAssembly::V128RegClass)
return WebAssembly::GET_LOCAL_V128;
+ if (RC == &WebAssembly::EXCEPT_REFRegClass)
+ return WebAssembly::GET_LOCAL_EXCEPT_REF;
llvm_unreachable("Unexpected register class");
}
@@ -116,6 +120,8 @@
return WebAssembly::SET_LOCAL_F64;
if (RC == &WebAssembly::V128RegClass)
return WebAssembly::SET_LOCAL_V128;
+ if (RC == &WebAssembly::EXCEPT_REFRegClass)
+ return WebAssembly::SET_LOCAL_EXCEPT_REF;
llvm_unreachable("Unexpected register class");
}
@@ -131,6 +137,8 @@
return WebAssembly::TEE_LOCAL_F64;
if (RC == &WebAssembly::V128RegClass)
return WebAssembly::TEE_LOCAL_V128;
+ if (RC == &WebAssembly::EXCEPT_REFRegClass)
+ return WebAssembly::TEE_LOCAL_EXCEPT_REF;
llvm_unreachable("Unexpected register class");
}
@@ -144,6 +152,8 @@
return MVT::f32;
if (RC == &WebAssembly::F64RegClass)
return MVT::f64;
+ if (RC == &WebAssembly::EXCEPT_REFRegClass)
+ return MVT::ExceptRef;
llvm_unreachable("unrecognized register class");
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
index 59bf1ad..f3ee6e7 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
@@ -127,6 +127,7 @@
case MVT::i64:
case MVT::f32:
case MVT::f64:
+ case MVT::ExceptRef:
return VT;
case MVT::f16:
return MVT::f32;
@@ -681,6 +682,10 @@
Opc = WebAssembly::ARGUMENT_v4f32;
RC = &WebAssembly::V128RegClass;
break;
+ case MVT::ExceptRef:
+ Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
+ RC = &WebAssembly::EXCEPT_REFRegClass;
+ break;
default:
return false;
}
@@ -770,6 +775,11 @@
IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32;
ResultReg = createResultReg(&WebAssembly::V128RegClass);
break;
+ case MVT::ExceptRef:
+ Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
+ : WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
+ ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
+ break;
default:
return false;
}
@@ -868,6 +878,10 @@
Opc = WebAssembly::SELECT_F64;
RC = &WebAssembly::F64RegClass;
break;
+ case MVT::ExceptRef:
+ Opc = WebAssembly::SELECT_EXCEPT_REF;
+ RC = &WebAssembly::EXCEPT_REFRegClass;
+ break;
default:
return false;
}
@@ -1274,6 +1288,9 @@
case MVT::v4f32:
Opc = WebAssembly::RETURN_v4f32;
break;
+ case MVT::ExceptRef:
+ Opc = WebAssembly::RETURN_EXCEPT_REF;
+ break;
default: return false;
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
index 6b45839..8874fe5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
@@ -72,6 +72,7 @@
defm : CALL<I64, "i64.">;
defm : CALL<F32, "f32.">;
defm : CALL<F64, "f64.">;
+ defm : CALL<EXCEPT_REF, "except_ref.">;
defm : SIMD_CALL<v16i8, "i8x16.">;
defm : SIMD_CALL<v8i16, "i16x8.">;
defm : SIMD_CALL<v4i32, "i32x4.">;
@@ -112,6 +113,9 @@
(CALL_v4i32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
(CALL_v4f32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(ExceptRef
+ (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
+ (CALL_EXCEPT_REF tglobaladdr:$callee)>;
def : Pat<(WebAssemblycall0 (WebAssemblywrapper tglobaladdr:$callee)),
(CALL_VOID tglobaladdr:$callee)>;
@@ -132,5 +136,8 @@
(CALL_v4i32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
(CALL_v4f32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
+def : Pat<(ExceptRef
+ (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
+ (CALL_EXCEPT_REF texternalsym:$callee)>;
def : Pat<(WebAssemblycall0 (WebAssemblywrapper texternalsym:$callee)),
(CALL_VOID texternalsym:$callee)>;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
index 1f1d438..18ffba7 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrControl.td
@@ -98,6 +98,7 @@
defm : RETURN<I64>;
defm : RETURN<F32>;
defm : RETURN<F64>;
+ defm : RETURN<EXCEPT_REF>;
defm : SIMD_RETURN<v16i8>;
defm : SIMD_RETURN<v8i16>;
defm : SIMD_RETURN<v4i32>;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrExceptRef.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrExceptRef.td
new file mode 100644
index 0000000..921e7ab
--- /dev/null
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrExceptRef.td
@@ -0,0 +1,29 @@
+// WebAssemblyInstrExceptRef.td-WebAssembly except_ref codegen --*- tablegen -*-
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief WebAssembly except_ref operand code-gen constructs.
+///
+//===----------------------------------------------------------------------===//
+
+let Defs = [ARGUMENTS] in {
+
+def SELECT_EXCEPT_REF : I<(outs EXCEPT_REF:$dst),
+ (ins EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond),
+ [(set EXCEPT_REF:$dst,
+ (select I32:$cond, EXCEPT_REF:$lhs,
+ EXCEPT_REF:$rhs))],
+ "except_ref.select\t$dst, $lhs, $rhs, $cond", 0x1b>;
+
+} // Defs = [ARGUMENTS]
+
+def : Pat<(select (i32 (setne I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
+ (SELECT_EXCEPT_REF EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond)>;
+def : Pat<(select (i32 (seteq I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
+ (SELECT_EXCEPT_REF EXCEPT_REF:$rhs, EXCEPT_REF:$lhs, I32:$cond)>;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
index f5a1be1..64695fb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
@@ -166,6 +166,7 @@
defm : ARGUMENT<I64>;
defm : ARGUMENT<F32>;
defm : ARGUMENT<F64>;
+defm : ARGUMENT<EXCEPT_REF>;
defm : SIMD_ARGUMENT<v16i8>;
defm : SIMD_ARGUMENT<v8i16>;
defm : SIMD_ARGUMENT<v4i32>;
@@ -232,6 +233,7 @@
defm : LOCAL<F32>;
defm : LOCAL<F64>;
defm : LOCAL<V128>, Requires<[HasSIMD128]>;
+defm : LOCAL<EXCEPT_REF>, Requires<[HasExceptionHandling]>;
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
def CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
@@ -267,3 +269,4 @@
include "WebAssemblyInstrFloat.td"
include "WebAssemblyInstrAtomics.td"
include "WebAssemblyInstrSIMD.td"
+include "WebAssemblyInstrExceptRef.td"
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
index 9088810..2110872 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
@@ -38,8 +38,8 @@
// since we otherwise don't need a physical register in those classes.
def F32_0 : WebAssemblyReg<"%f32.0">;
def F64_0 : WebAssemblyReg<"%f64.0">;
-
def V128_0: WebAssemblyReg<"%v128">;
+def EXCEPT_REF_0 : WebAssemblyReg<"%except_ref.0">;
// The value stack "register". This is an opaque entity which serves to order
// uses and defs that must remain in LIFO order.
@@ -59,4 +59,4 @@
def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;
-
+def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;