commit 0e7d8698b5251f42286cd71bd1667cbafe761be1
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Jul 24 16:05:53 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Jul 24 16:05:53 2019 +0000
tree 17f101f25a16e1cfd0c0bbe40a6ee37a248c03f0
parent 10dad95a75592717d2f7c0ebc181fb8a970a8df7

AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting exts

The G_ANYEXT handling can end up reaching selectCOPY, which mutates
the instruction in place.

llvm-svn: 366915

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index a68817d..5db2e6f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1006,6 +1006,7 @@
     BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
       .addImm(0)
       .addImm(Signed ? -1 : 1);
+    I.eraseFromParent();
     return RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
   }
 
@@ -1020,6 +1021,7 @@
       .addImm(0)               // src1_modifiers
       .addImm(Signed ? -1 : 1) // src1
       .addUse(SrcReg);
+    I.eraseFromParent();
     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
   }
 
@@ -1036,6 +1038,7 @@
       BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
         .addImm(Mask)
         .addReg(SrcReg);
+      I.eraseFromParent();
       return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
     }
 
@@ -1045,6 +1048,7 @@
       .addReg(SrcReg)
       .addImm(0) // Offset
       .addImm(SrcSize); // Width
+    I.eraseFromParent();
     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
   }
 
@@ -1057,6 +1061,7 @@
         AMDGPU::S_SEXT_I32_I8 : AMDGPU::S_SEXT_I32_I16;
       BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg)
         .addReg(SrcReg);
+      I.eraseFromParent();
       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
     }
 
@@ -1081,6 +1086,7 @@
         .addReg(ExtReg)
         .addImm(SrcSize << 16);
 
+      I.eraseFromParent();
       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
     }
 
@@ -1095,6 +1101,7 @@
         .addImm(SrcSize << 16);
     }
 
+    I.eraseFromParent();
     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
   }
 
@@ -1369,12 +1376,7 @@
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_ANYEXT:
-    if (selectG_SZA_EXT(I)) {
-      I.eraseFromParent();
-      return true;
-    }
-
-    return false;
+    return selectG_SZA_EXT(I);
   case TargetOpcode::G_BRCOND:
     return selectG_BRCOND(I);
   case TargetOpcode::G_FRAME_INDEX: