ARM64: [su]xtw use W regs as inputs, not X regs.
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.
PR19455 and rdar://16650642
llvm-svn: 206495
diff --git a/llvm/test/CodeGen/ARM64/extend.ll b/llvm/test/CodeGen/ARM64/extend.ll
index 4d20543..afcaca2 100644
--- a/llvm/test/CodeGen/ARM64/extend.ll
+++ b/llvm/test/CodeGen/ARM64/extend.ll
@@ -5,7 +5,7 @@
; CHECK: foo
; CHECK: adrp x[[REG:[0-9]+]], _array@GOTPAGE
; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _array@GOTPAGEOFF]
-; CHECK: ldrsw x0, [x[[REG1]], x0, sxtw #2]
+; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
; CHECK: ret
%idxprom = sext i32 %i to i64
%arrayidx = getelementptr inbounds [0 x i32]* @array, i64 0, i64 %idxprom