[FastISel][AArch64] Use the zero register for stores.
Use the zero register directly when possible to avoid an unnecessary register
copy and a wasted register at -O0. This also uses integer stores to store a
positive floating-point zero. This saves us from materializing the positive zero
in a register and then storing it.
llvm-svn: 216617
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll b/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
index 222c960..86ba400 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
-; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
+; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
+; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; Load / Store Base Register only
define zeroext i1 @load_breg_i1(i1* %a) {
@@ -53,11 +53,18 @@
define void @store_breg_i1(i1* %a) {
; CHECK-LABEL: store_breg_i1
-; CHECK: strb {{wzr|w[0-9]+}}, [x0]
+; CHECK: strb wzr, [x0]
store i1 0, i1* %a
ret void
}
+define void @store_breg_i1_2(i1* %a) {
+; CHECK-LABEL: store_breg_i1_2
+; CHECK: strb {{w[0-9]+}}, [x0]
+ store i1 true, i1* %a
+ ret void
+}
+
define void @store_breg_i8(i8* %a) {
; CHECK-LABEL: store_breg_i8
; CHECK: strb wzr, [x0]
@@ -88,14 +95,14 @@
define void @store_breg_f32(float* %a) {
; CHECK-LABEL: store_breg_f32
-; CHECK: str {{wzr|s[0-9]+}}, [x0]
+; CHECK: str wzr, [x0]
store float 0.0, float* %a
ret void
}
define void @store_breg_f64(double* %a) {
; CHECK-LABEL: store_breg_f64
-; CHECK: str {{xzr|d[0-9]+}}, [x0]
+; CHECK: str xzr, [x0]
store double 0.0, double* %a
ret void
}
@@ -426,7 +433,7 @@
; Load Scaled Register Offset + Immediate Offset + Sign/Zero extension
define i64 @load_sext_shift_offreg_imm1(i32 %a) {
; CHECK-LABEL: load_sext_shift_offreg_imm1
-; CHECK: sbfiz [[REG:x[0-9]+]], x0, #3, #32
+; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
%1 = sext i32 %a to i64
%2 = shl i64 %1, 3