[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Legalize and emit code for:
* xscvsdqp
* xscvudqp
Differential Revision: https://reviews.llvm.org/D45230
llvm-svn: 329931
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 04a13e2..d84f828 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2512,7 +2512,12 @@
// Convert (Un)Signed DWord -> QP
def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
+ def : Pat<(f128 (sint_to_fp i64:$src)),
+ (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+
def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>;
+ def : Pat<(f128 (uint_to_fp i64:$src)),
+ (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
let UseVSXReg = 1 in {
//===--------------------------------------------------------------------===//
@@ -3117,6 +3122,17 @@
(COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>;
def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
(f32 (DFLOADf32 ixaddr:$src))>;
+
+ // Convert (Un)Signed DWord in memory -> QP
+ def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))),
+ (f128 (XSCVSDQP (LXSDX xaddr:$src)))>;
+ def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))),
+ (f128 (XSCVSDQP (LXSD ixaddr:$src)))>;
+ def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))),
+ (f128 (XSCVUDQP (LXSDX xaddr:$src)))>;
+ def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))),
+ (f128 (XSCVUDQP (LXSD ixaddr:$src)))>;
+
} // end HasP9Vector, AddedComplexity
let Predicates = [HasP9Vector] in {