| commit | 10511a493e01d2ae46830e3b0f872cf733f940d8 | [log] [tgz] |
|---|---|---|
| author | Ranjeet Singh <Ranjeet.Singh@arm.com> | Mon Jun 08 21:32:16 2015 +0000 |
| committer | Ranjeet Singh <Ranjeet.Singh@arm.com> | Mon Jun 08 21:32:16 2015 +0000 |
| tree | 80abf89db34b22517371a182fac27d6032c1eb33 | |
| parent | cbed1e4f793589107a59b6559515253ff610438f [diff] [blame] |
[AArch64] AsmParser should be case insensitive about accepting vector register names. Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 41615b6..063c053 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1764,7 +1764,7 @@ /// } static unsigned matchVectorRegName(StringRef Name) { - return StringSwitch<unsigned>(Name) + return StringSwitch<unsigned>(Name.lower()) .Case("v0", AArch64::Q0) .Case("v1", AArch64::Q1) .Case("v2", AArch64::Q2)