commit 11284ea499c5f2f1ef81b162503e5b4928d152f7
author Bill Wendling <isanbard@gmail.com> Sun Aug 31 01:13:31 2008 +0000
committer Bill Wendling <isanbard@gmail.com> Sun Aug 31 01:13:31 2008 +0000
tree 344283da4284c4c6375dbc4d72fceac4ad1f765e
parent 4822a7ac8ada327008a4792db36fb645b003d02f

Another situation where ROTR is cheaper than ROTL.

llvm-svn: 55577

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2521609..e414fdf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2044,10 +2044,10 @@
     if (ConstantSDNode *SUBC = 
           dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
       if (SUBC->getAPIntValue() == OpSizeInBits) {
-        if (HasROTL)
-          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
-        else
+        if (HasROTR)
           return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
+        else
+          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
       }
     }
   }