GlobalISel: use G_TYPE to annotate physregs with a type.
More preparation for dropping source types from MachineInstrs: regsters coming
out of already-selected code (i.e. non-generic instructions) don't have a type,
but that information is needed so we must add it manually.
This is done via a new G_TYPE instruction.
llvm-svn: 280292
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 9d1c1e7..4ce643d 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -25,9 +25,9 @@
// First step is to marshall all the function's parameters into the correct
// physregs and memory locations. Gather the sequence of argument types that
// we'll pass to the assigner function.
- SmallVector<MVT, 8> ArgTys;
+ SmallVector<Type *, 8> ArgTys;
for (auto &Arg : CI.arg_operands())
- ArgTys.push_back(MVT::getVT(Arg->getType()));
+ ArgTys.push_back(Arg->getType());
MachineOperand Callee = MachineOperand::CreateImm(0);
if (Function *F = CI.getCalledFunction())
@@ -35,6 +35,6 @@
else
Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
- return lowerCall(MIRBuilder, Callee, MVT::getVT(CI.getType()),
+ return lowerCall(MIRBuilder, Callee, CI.getType(),
ResReg ? ResReg : ArrayRef<unsigned>(), ArgTys, ArgRegs);
}
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index df48c42..da18b03 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -168,6 +168,11 @@
.addUse(CarryIn);
}
+MachineInstrBuilder MachineIRBuilder::buildType(LLT Ty,
+ unsigned Res, unsigned Op) {
+ return buildInstr(TargetOpcode::G_TYPE, Ty).addDef(Res).addUse(Op);
+}
+
MachineInstrBuilder MachineIRBuilder::buildAnyExt(ArrayRef<LLT> Tys,
unsigned Res, unsigned Op) {
validateTruncExt(Tys, true);
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
index 9787227..18db91c 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
@@ -104,7 +104,8 @@
default:
return UnableToLegalize;
case TargetOpcode::G_FREM: {
- MVT Ty = MVT::getFloatingPointVT(MI.getType().getSizeInBits());
+ auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
+ Type *Ty = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
const char *Name =
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
index baef765..cc3d4ec 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
@@ -30,6 +30,9 @@
DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
DefaultActions[TargetOpcode::G_TRUNC] = Legal;
+ // G_TYPE is essentially an annotated COPY so it's always legal.
+ DefaultActions[TargetOpcode::G_TYPE] = Legal;
+
DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 5e55417..5a950ff1 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -224,7 +224,8 @@
bool CompleteMapping = true;
// For copies we want to walk over the operands and try to find one
// that has a register bank.
- bool isCopyLike = MI.isCopy() || MI.isPHI();
+ bool isCopyLike =
+ MI.isCopy() || MI.isPHI() || MI.getOpcode() == TargetOpcode::G_TYPE;
// Remember the register bank for reuse for copy-like instructions.
const RegisterBank *RegBank = nullptr;
// Remember the size of the register for reuse for copy-like instructions.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 479c9e7..0b8a85d 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -903,7 +903,8 @@
}
// Generic opcodes must not have physical register operands.
- if (isPreISelGenericOpcode(MCID.getOpcode())) {
+ if (isPreISelGenericOpcode(MCID.getOpcode()) &&
+ MCID.getOpcode() != TargetOpcode::G_TYPE) {
for (auto &Op : MI->operands()) {
if (Op.isReg() && TargetRegisterInfo::isPhysicalRegister(Op.getReg()))
report("Generic instruction cannot have physical register", MI);