AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds
Summary:
For some reason instructions are being inserted in the wrong order with some
builds. I'm not sure why this is happening.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D29325
llvm-svn: 293639
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 6e5e982..d133851 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -84,13 +84,19 @@
DebugLoc DL = I.getDebugLoc();
+ MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
+ MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
+
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
- .add(getSubOperand64(I.getOperand(1), AMDGPU::sub0))
- .add(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
+ .add(Lo1)
+ .add(Lo2);
+
+ MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
+ MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
- .add(getSubOperand64(I.getOperand(1), AMDGPU::sub1))
- .add(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
+ .add(Hi1)
+ .add(Hi2);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
.addReg(DstLo)