[Hexagon] Implement RDF-based post-RA optimizations
- Handle simple cases of register copies (what current RDF CP allows).
- Hexagon-specific dead code elimination: handles dead address updates
in post-increment instructions.
llvm-svn: 257504
diff --git a/llvm/test/CodeGen/Hexagon/postinc-offset.ll b/llvm/test/CodeGen/Hexagon/postinc-offset.ll
index 5e0f475..cf8c4e5 100644
--- a/llvm/test/CodeGen/Hexagon/postinc-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-offset.ll
@@ -1,4 +1,5 @@
-; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 -rdf-opt=0 \
+; RUN: < %s | FileCheck %s
; CHECK: {
; CHECK: ={{ *}}memd([[REG0:(r[0-9]+)]]{{ *}}++{{ *}}#8)
diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy.ll b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
new file mode 100644
index 0000000..96153ca
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
@@ -0,0 +1,54 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Check that
+; {
+; r1 = r0
+; }
+; {
+; r0 = memw(r1 + #0)
+; }
+; was copy-propagated to
+; {
+; r1 = r0
+; r0 = memw(r0 + #0)
+; }
+;
+; CHECK-LABEL: LBB0_1
+; CHECK: [[DST:r[0-9]+]] = [[SRC:r[0-9]+]]
+; CHECK-DAG: memw([[SRC]]
+; CHECK-DAG-NOT: memw([[DST]]
+; CHECK-LABEL: LBB0_2
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+%union.t = type { %struct.t, [64 x i8] }
+%struct.t = type { [12 x i8], %struct.r*, double }
+%struct.r = type opaque
+
+define %union.t* @foo(%union.t* %chain) nounwind readonly {
+entry:
+ %tobool = icmp eq %union.t* %chain, null
+ br i1 %tobool, label %if.end, label %while.cond.preheader
+
+while.cond.preheader: ; preds = %entry
+ br label %while.cond
+
+while.cond: ; preds = %while.cond.preheader, %while.cond
+ %chain.addr.0 = phi %union.t* [ %0, %while.cond ], [ %chain, %while.cond.preheader ]
+ %chain1 = bitcast %union.t* %chain.addr.0 to %union.t**
+ %0 = load %union.t*, %union.t** %chain1, align 4, !tbaa !0
+ %tobool2 = icmp eq %union.t* %0, null
+ br i1 %tobool2, label %if.end.loopexit, label %while.cond
+
+if.end.loopexit: ; preds = %while.cond
+ br label %if.end
+
+if.end: ; preds = %if.end.loopexit, %entry
+ %chain.addr.1 = phi %union.t* [ null, %entry ], [ %chain.addr.0, %if.end.loopexit ]
+ ret %union.t* %chain.addr.1
+}
+
+!0 = !{!"any pointer", !1}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}
diff --git a/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll b/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll
new file mode 100644
index 0000000..3762c79
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK-NOT: ={{.*}}add
+; CHECK-NOT: mem{{[bdhwu]}}
+
+define void @main() #0 {
+entry:
+ br label %body
+
+body:
+ %ip_vec30 = phi <2 x i32> [ %ip_vec, %body ], [ zeroinitializer, %entry ]
+ %scevgep.phi = phi i32* [ %scevgep.inc, %body ], [ undef, %entry ]
+ %polly.indvar = phi i32 [ %polly.indvar_next, %body ], [ 0, %entry ]
+ %vector_ptr = bitcast i32* %scevgep.phi to <2 x i32>*
+ %_p_vec_full = load <2 x i32>, <2 x i32>* %vector_ptr, align 8
+ %ip_vec = add <2 x i32> %_p_vec_full, %ip_vec30
+ %polly.indvar_next = add nsw i32 %polly.indvar, 2
+ %polly.loop_cond = icmp slt i32 %polly.indvar, 4
+ %scevgep.inc = getelementptr i32, i32* %scevgep.phi, i32 2
+ br i1 %polly.loop_cond, label %body, label %exit
+
+exit:
+ %0 = extractelement <2 x i32> %ip_vec, i32 1
+ ret void
+
+}
+
+attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!0 = !{!"int", !1}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}