[X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI
This reduces the total number of generated scheduler classes from 5404 to 5316.
llvm-svn: 327815
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index e4cbe7d..8efc233 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -599,8 +599,7 @@
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "ADC(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADCX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADOX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)ri8")>;
@@ -619,24 +618,17 @@
def: InstRW<[BWWriteResGroup6], (instregex "JMP_1")>;
def: InstRW<[BWWriteResGroup6], (instregex "JMP_4")>;
def: InstRW<[BWWriteResGroup6], (instregex "RORX(32|64)ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SAR8r1")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SAR(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SAR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SARX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SBB(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHL8r1")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHL8ri")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SHL(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SHL(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHLX(32|64)rr")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHR8r1")>;
-def: InstRW<[BWWriteResGroup6], (instregex "SHR8ri")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SHR(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup6], (instregex "SHR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHRX(32|64)rr")>;
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
@@ -859,48 +851,35 @@
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "ADD8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "AND8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;
def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "CMP8rr")>;
def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
-def: InstRW<[BWWriteResGroup9], (instregex "DEC(16|32|64)r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "DEC8r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "INC(16|32|64)r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "INC8r")>;
+def: InstRW<[BWWriteResGroup9], (instregex "DEC(8|16|32|64)r")>;
+def: InstRW<[BWWriteResGroup9], (instregex "INC(8|16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;
-def: InstRW<[BWWriteResGroup9], (instregex "MOV(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "MOV(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "MOV8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr8")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVZX(16|32|64)rr16")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVZX(16|32|64)rr8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "NEG(16|32|64)r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "NEG8r")>;
+def: InstRW<[BWWriteResGroup9], (instregex "NEG(8|16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;
-def: InstRW<[BWWriteResGroup9], (instregex "NOT(16|32|64)r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "NOT8r")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "NOT(8|16|32|64)r")>;
+def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "OR8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SAHF")>;
def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m")>;
def: InstRW<[BWWriteResGroup9], (instregex "SIDT64m")>;
@@ -908,22 +887,17 @@
def: InstRW<[BWWriteResGroup9], (instregex "SMSW16m")>;
def: InstRW<[BWWriteResGroup9], (instregex "STC")>;
def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "SUB8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
-def: InstRW<[BWWriteResGroup9], (instregex "TEST(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "TEST8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr")>;
+def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR8ri")>;
-def: InstRW<[BWWriteResGroup9], (instregex "XOR8rr")>;
def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
let Latency = 1;
@@ -1027,14 +1001,10 @@
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[BWWriteResGroup13], (instregex "ROL(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROL(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROL8r1")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROL8ri")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROR(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROR(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROR8r1")>;
-def: InstRW<[BWWriteResGroup13], (instregex "ROR8ri")>;
+def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup13], (instregex "ROR(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup13], (instregex "ROR(8|16|32|64)ri")>;
def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
let Latency = 2;
@@ -1362,8 +1332,7 @@
let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def: InstRW<[BWWriteResGroup30], (instregex "XADD(16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup30], (instregex "XADD8rr")>;
+def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup30], (instregex "XCHG8rr")>;
def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
@@ -1429,30 +1398,21 @@
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[BWWriteResGroup35], (instregex "RCL(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCL(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCL8r1")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCL8ri")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCR(16|32|64)r1")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCR(16|32|64)ri")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCR8r1")>;
-def: InstRW<[BWWriteResGroup35], (instregex "RCR8ri")>;
+def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup35], (instregex "RCR(8|16|32|64)r1")>;
+def: InstRW<[BWWriteResGroup35], (instregex "RCR(8|16|32|64)ri")>;
def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[BWWriteResGroup36], (instregex "ROL(16|32|64)rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "ROL8rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "ROR(16|32|64)rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "ROR8rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "SAR(16|32|64)rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "SAR8rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "SHL(16|32|64)rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "SHL8rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "SHR(16|32|64)rCL")>;
-def: InstRW<[BWWriteResGroup36], (instregex "SHR8rCL")>;
+def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL")>;
+def: InstRW<[BWWriteResGroup36], (instregex "ROR(8|16|32|64)rCL")>;
+def: InstRW<[BWWriteResGroup36], (instregex "SAR(8|16|32|64)rCL")>;
+def: InstRW<[BWWriteResGroup36], (instregex "SHL(8|16|32|64)rCL")>;
+def: InstRW<[BWWriteResGroup36], (instregex "SHR(8|16|32|64)rCL")>;
def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
let Latency = 3;
@@ -2000,16 +1960,14 @@
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup63], (instregex "ADC(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "ADC8rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADCX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADOX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup63], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "RORX(32|64)mi")>;
def: InstRW<[BWWriteResGroup63], (instregex "SARX(32|64)rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SBB(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup63], (instregex "SBB8rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "SBB(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SHLX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SHRX(32|64)rm")>;
@@ -2175,27 +2133,18 @@
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup66], (instregex "ADD(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "ADD8rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "AND(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "AND8rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP8mi")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP8mr")>;
-def: InstRW<[BWWriteResGroup66], (instregex "CMP8rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "OR(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "OR8rm")>;
+def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm")>;
+def: InstRW<[BWWriteResGroup66], (instregex "AND(8|16|32|64)rm")>;
+def: InstRW<[BWWriteResGroup66], (instregex "CMP(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup66], (instregex "CMP(8|16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup66], (instregex "CMP(8|16|32|64)rm")>;
+def: InstRW<[BWWriteResGroup66], (instregex "OR(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
-def: InstRW<[BWWriteResGroup66], (instregex "SUB(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "SUB8rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "TEST(16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup66], (instregex "SUB(8|16|32|64)rm")>;
+def: InstRW<[BWWriteResGroup66], (instregex "TEST(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "TEST8mi")>;
-def: InstRW<[BWWriteResGroup66], (instregex "TEST8mr")>;
-def: InstRW<[BWWriteResGroup66], (instregex "XOR(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup66], (instregex "XOR8rm")>;
+def: InstRW<[BWWriteResGroup66], (instregex "XOR(8|16|32|64)rm")>;
def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 6;
@@ -2220,54 +2169,34 @@
def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup69], (instregex "BTR(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup69], (instregex "BTS(16|32|64)mi8")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SAR(16|32|64)m1")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SAR(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SAR8m1")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SAR8mi")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHL(16|32|64)m1")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHL(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHL8m1")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHL8mi")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHR(16|32|64)m1")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHR(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHR8m1")>;
-def: InstRW<[BWWriteResGroup69], (instregex "SHR8mi")>;
+def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m1")>;
+def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup69], (instregex "SHL(8|16|32|64)m1")>;
+def: InstRW<[BWWriteResGroup69], (instregex "SHL(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup69], (instregex "SHR(8|16|32|64)m1")>;
+def: InstRW<[BWWriteResGroup69], (instregex "SHR(8|16|32|64)mi")>;
def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
-def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "ADD8mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "ADD8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "AND8mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "AND8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "DEC(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "DEC8m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "INC(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "INC8m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "NEG(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "NEG8m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "NOT(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "NOT8m")>;
-def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "OR8mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "OR8mr")>;
+def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup70], (instregex "AND(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup70], (instregex "AND(8|16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup70], (instregex "DEC(8|16|32|64)m")>;
+def: InstRW<[BWWriteResGroup70], (instregex "INC(8|16|32|64)m")>;
+def: InstRW<[BWWriteResGroup70], (instregex "NEG(8|16|32|64)m")>;
+def: InstRW<[BWWriteResGroup70], (instregex "NOT(8|16|32|64)m")>;
+def: InstRW<[BWWriteResGroup70], (instregex "OR(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup70], (instregex "OR(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[BWWriteResGroup70], (instregex "PUSH(16|32|64)rmm")>;
-def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "SUB8mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "SUB8mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup70], (instregex "XOR8mi")>;
-def: InstRW<[BWWriteResGroup70], (instregex "XOR8mr")>;
+def: InstRW<[BWWriteResGroup70], (instregex "SUB(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup70], (instregex "SUB(8|16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup70], (instregex "XOR(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup70], (instregex "XOR(8|16|32|64)mr")>;
def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 6;
@@ -2738,54 +2667,39 @@
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[BWWriteResGroup97], (instregex "RCL(16|32|64)m1")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCL(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCL8m1")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCL8mi")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCR(16|32|64)m1")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCR(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCR8m1")>;
-def: InstRW<[BWWriteResGroup97], (instregex "RCR8mi")>;
+def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1")>;
+def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup97], (instregex "RCR(8|16|32|64)m1")>;
+def: InstRW<[BWWriteResGroup97], (instregex "RCR(8|16|32|64)mi")>;
def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
let ResourceCycles = [1,1,2,1];
}
-def: InstRW<[BWWriteResGroup98], (instregex "ROR(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup98], (instregex "ROR8mCL")>;
+def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
-def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup99], (instregex "ADC8mi")>;
-def: InstRW<[BWWriteResGroup99], (instregex "XCHG(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup99], (instregex "XCHG8rm")>;
+def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[BWWriteResGroup100], (instregex "ADC(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup100], (instregex "ADC8mr")>;
-def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(16|32|64)rm")>;
-def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG8rm")>;
-def: InstRW<[BWWriteResGroup100], (instregex "ROL(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "ROL8mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SAR(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SAR8mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mr")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SBB8mi")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SBB8mr")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SHL(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SHL8mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SHR(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup100], (instregex "SHR8mCL")>;
+def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm")>;
+def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SAR(8|16|32|64)mCL")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SBB(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SBB(8|16|32|64)mr")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SHL(8|16|32|64)mCL")>;
+def: InstRW<[BWWriteResGroup100], (instregex "SHR(8|16|32|64)mCL")>;
def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 9;
@@ -3313,8 +3227,7 @@
let NumMicroOps = 10;
let ResourceCycles = [1,1,1,4,1,2];
}
-def: InstRW<[BWWriteResGroup149], (instregex "RCL(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup149], (instregex "RCL8mCL")>;
+def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 16;
@@ -3401,8 +3314,7 @@
let NumMicroOps = 11;
let ResourceCycles = [2,1,1,3,1,3];
}
-def: InstRW<[BWWriteResGroup160], (instregex "RCR(16|32|64)mCL")>;
-def: InstRW<[BWWriteResGroup160], (instregex "RCR8mCL")>;
+def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 19;
@@ -3688,36 +3600,30 @@
let NumMicroOps = 8;
let ResourceCycles = [2,2,2,1,1];
}
-def: InstRW<[BWWriteResGroup190], (instregex "DIV(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup190], (instregex "DIV8m")>;
+def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
let Latency = 34;
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
-def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)ri")>;
-def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)rr")>;
-def: InstRW<[BWWriteResGroup191], (instregex "IN8ri")>;
-def: InstRW<[BWWriteResGroup191], (instregex "IN8rr")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri")>;
+def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)rr")>;
def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
let Latency = 35;
let NumMicroOps = 8;
let ResourceCycles = [2,2,2,1,1];
}
-def: InstRW<[BWWriteResGroup193], (instregex "IDIV(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup193], (instregex "IDIV8m")>;
+def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
-def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)ir")>;
-def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)rr")>;
-def: InstRW<[BWWriteResGroup194], (instregex "OUT8ir")>;
-def: InstRW<[BWWriteResGroup194], (instregex "OUT8rr")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir")>;
+def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)rr")>;
def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
let Latency = 40;