commit 143b0dff319c23324f60a3536ef37c536c0a6c65
author Lauro Ramos Venancio <lauro.venancio@gmail.com> Tue Mar 27 16:19:21 2007 +0000
committer Lauro Ramos Venancio <lauro.venancio@gmail.com> Tue Mar 27 16:19:21 2007 +0000
tree 93ea08948a49463f73e694dcd1593a613c381a33
parent 37a0bfe1288f3a27111468df0a5d3b5af94aed8c

bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.

llvm-svn: 35381

llvm/lib/Target/ARM/ARMISelLowering.cpp

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cb3d923..50ac5e9 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -555,10 +555,10 @@
     CallOpc = (isDirect || Subtarget->hasV5TOps())
       ? ARMISD::CALL : ARMISD::CALL_NOLINK;
   }
-  if (CallOpc == ARMISD::CALL_NOLINK) {
-    // On CALL_NOLINK we must move PC to LR
+  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
+    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
     Chain = DAG.getCopyToReg(Chain, ARM::LR,
-                             DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
     InFlag = Chain.getValue(1);
   }
 

llvm/lib/Target/ARM/ARMInstrInfo.td

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 201f65c..36d2e4a 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -370,6 +370,8 @@
   : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AI4<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AIx2<dag ops, string asm, list<dag> pattern>
+  : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
 class AI1x2<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
 
@@ -546,9 +548,9 @@
                [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
   let Uses = [LR] in {
     // ARMv4T
-    def BX : AI<(ops GPR:$dst, variable_ops),
-                "bx $dst",
-                [(ARMcall_nolink GPR:$dst)]>;
+    def BX : AIx2<(ops GPR:$dst, variable_ops),
+                  "mov lr, pc\n\tbx $dst",
+                  [(ARMcall_nolink GPR:$dst)]>;
   }
 }
 

llvm/lib/Target/ARM/ARMInstrThumb.td

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index a1f03bd..3c7cd03 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -189,12 +189,10 @@
   def tBLXr : TI<(ops GPR:$dst, variable_ops),
                   "blx $dst",
                   [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
-  let Uses = [LR] in {
-    // ARMv4T
-    def tBX : TI<(ops GPR:$dst, variable_ops),
-                  "bx $dst",
+  // ARMv4T
+  def tBX : TIx2<(ops GPR:$dst, variable_ops),
+                  "cpy lr, pc\n\tbx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
-  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {