| commit | 160f73e36ff1ba9cf854f68f1f7e2bd80dfe3ec2 | [log] [tgz] |
|---|---|---|
| author | Colin LeMahieu <colinl@codeaurora.org> | Tue Nov 03 00:21:19 2015 +0000 |
| committer | Colin LeMahieu <colinl@codeaurora.org> | Tue Nov 03 00:21:19 2015 +0000 |
| tree | fda7a0c30517e94fd8b99a9b865b743be8479712 | |
| parent | c7ed52f2ba04d7e9588f9eb7cda023d8321a07f1 [diff] [blame] |
[Hexagon] Fixing mistaken case fallthrough. llvm-svn: 251867
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 8f9d03f..ef18877 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -1054,6 +1054,7 @@ operand = getDRegFromSubinstEncoding(inst & 0x7); Op = MCOperand::createReg(operand); MI->addOperand(Op); + break; case Hexagon::V4_SS2_storeh_io: // Rs 7-4, u 10-8{3_1}, Rt 3-0 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);