[AMDGPU] Disassembler: Support for all VOP1 instructions.
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget:
VGPR_32 and VReg_64 operand register classes
VS_32 and VS_64 operand register classes with inline and literal constants
Tests for VOP1 instructions.
Patch by: skolton
Reviewers: arsenm, tstellarAMD
Review: http://reviews.llvm.org/D17194
llvm-svn: 261878
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index 9681ea2..273089d 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -25,9 +25,14 @@
class MCSubtargetInfo;
class AMDGPUDisassembler : public MCDisassembler {
+ private:
+ /// true if 32-bit literal constant is placed after instruction
+ mutable bool HasLiteral;
+ mutable ArrayRef<uint8_t> Bytes;
+
public:
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
- MCDisassembler(STI, Ctx) {}
+ MCDisassembler(STI, Ctx), HasLiteral(false) {}
~AMDGPUDisassembler() {}
@@ -35,23 +40,41 @@
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &WS, raw_ostream &CS) const override;
- /// Decode inline float value in VSrc field
- DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
- /// Decode inline integer value in VSrc field
- DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
+ /// Decode inline float value in SRC field
+ DecodeStatus DecodeImmedFloat(unsigned Imm, uint32_t &F) const;
+ /// Decode inline double value in SRC field
+ DecodeStatus DecodeImmedDouble(unsigned Imm, uint64_t &D) const;
+ /// Decode inline integer value in SRC field
+ DecodeStatus DecodeImmedInteger(unsigned Imm, int64_t &I) const;
/// Decode VGPR register
- DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
+ DecodeStatus DecodeVgprRegister(unsigned Val, unsigned &RegID,
+ unsigned Size = 32) const;
/// Decode SGPR register
- DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
- /// Decode register in VSrc field
- DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
+ DecodeStatus DecodeSgprRegister(unsigned Val, unsigned &RegID,
+ unsigned Size = 32) const;
+ /// Decode 32-bit register in SRC field
+ DecodeStatus DecodeSrc32Register(unsigned Val, unsigned &RegID) const;
+ /// Decode 64-bit register in SRC field
+ DecodeStatus DecodeSrc64Register(unsigned Val, unsigned &RegID) const;
- DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
+ /// Decode literal constant after instruction
+ DecodeStatus DecodeLiteralConstant(MCInst &Inst, uint64_t &Literal) const;
+
+ DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
+ uint64_t Addr) const;
+
+ DecodeStatus DecodeVSRegisterClass(MCInst &Inst, unsigned Imm,
+ uint64_t Addr, bool Is32) const;
+
+ DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
uint64_t Addr) const;
- DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
+ DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
+ uint64_t Addr) const;
+
+ DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
uint64_t Addr) const;
};
} // namespace llvm
-#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
+#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H