R600/SI: Move SIFixSGPRCopies to inst selector passes
This should expose more of the actually used VALU
instructions to the machine optimization passes.
This also should help getting i1 handling into a better state.
For not entirly understood reasons, this fixes the split-scalar-i64-add.ll
test where a 64-bit add would only partially be moved to the VALU
resulting in use of undefined VCC.
llvm-svn: 222256
diff --git a/llvm/test/CodeGen/R600/i1-copy-phi.ll b/llvm/test/CodeGen/R600/i1-copy-phi.ll
index d987d73..bfa8672 100644
--- a/llvm/test/CodeGen/R600/i1-copy-phi.ll
+++ b/llvm/test/CodeGen/R600/i1-copy-phi.ll
@@ -1,6 +1,14 @@
-; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; SI-LABEL: {{^}}br_i1_phi:
+; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
+; SI: s_and_saveexec_b64
+; SI: s_xor_b64
+; SI: v_mov_b32_e32 [[REG]], -1{{$}}
+; SI: v_cmp_ne_i32_e64 {{s\[[0-9]+:[0-9]+\]}}, [[REG]], 0
+; SI: s_and_saveexec_b64
+; SI: s_xor_b64
+; SI: s_endpgm
define void @br_i1_phi(i32 %arg, i1 %arg1) #0 {
bb:
br i1 %arg1, label %bb2, label %bb3