[RISCV] Add inline asm constraint A for RISC-V
This allows the constraint A to be used in inline asm for RISC-V, which
allows an address held in a register to be used.
This patch adds the minimal amount of code required to get operands with
the right constraints to compile.
Differential Revision: https://reviews.llvm.org/D54295
llvm-svn: 369093
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index a634ba6..d1166d9 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@
// A floating-point register.
Info.setAllowsRegister();
return true;
+ case 'A':
+ // An address that is held in a general-purpose register.
+ Info.setAllowsMemory();
+ return true;
}
}